Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
PicoBlaze - Program RAM Access for an Interactive Monitor
You can give PicoBlaze a live interactive monitor without reconfiguring the FPGA. Victor Yurkovsky walks through using the BRAM's unused port by replacing the assembler template with a dual-ported RAMB16_S18_S18 and exposing maddr, mfromram, mtoram and mwr ports. The post includes IO decoding and a PicoBlaze assembly test to read, write and increment program memory over a serial link.
MyHDL ... MyPWM
Christopher Felton presents a compact MyHDL PWM engine designed to be configured at design time and targeted for FPGA synthesis. The module derives PWM bit width from the system clock frequency and desired pwm_frequency, truncates inputs when necessary, and prints parameter summaries for different clock/pwm combinations. The post includes the full MyHDL source and a simulation waveform showing the input signal and the modulated output, making it easy to reproduce.
StrangeCPU #4. Microcode
Victor Yurkovsky shows how a sliding-window opcode scheme turns tiny 8–9 bit tokens into wide microinstructions on an FPGA, letting you pack rich behavior into compact code. The post explains visibility ranges, instruction-data representation, and a low-cost way to add a Red-program counter so runs of microcode execute efficiently with minimal hardware overhead.
Yet another PWM
The provided record for Anton Babushkin’s post “Yet another PWM” contains no article body, so the actual technical content is not available for review. The title and site context indicate the post concerns pulse-width modulation (PWM), but specific implementation details, language, or examples cannot be confirmed from the supplied input. This metadata therefore documents the absence of content, recommends steps to recover the original post, and flags that any downstream use (tagging, excerpts, or code extraction) must wait until the full text is retrieved from FPGARelated’s archive or the author’s copy to avoid misrepresentation.
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Victor Yurkovsky extends his sliding-window token machine idea to instruction decoding, showing how 8/9-bit tokens can index shared "Blue" memory as 32-bit literals, call targets, or decoded instructions. The approach makes instructions dynamic entries that slide with the window, enabling rare opcodes to be synthesized on demand and reducing fixed opcode bloat. He also covers the 0-bit window (the stack), FPGA BRAM tagging, and the latency trade-offs.
StrangeCPU #2. Sliding Window Token Machines
Victor Yurkovsky walks through a surprising CPU design that expands tiny 8/9-bit tokens into full 32-bit call targets using a sliding-window pointer table. The article explains the red/blue memory model, compilation tradeoffs like table overrun and under-run, literal factoring, FPGA scaling, and even includes an ARM Cortex-M implementation snippet to show how the interpreter works in practice.
StrangeCPU #1. A new CPU
This post rethinks call instructions by factoring call targets out of every callsite and replacing them with tiny tokens. Victor Yurkovsky introduces StrangeCPU, a bytecode CPU that uses 8-bit tokens plus a static sliding-window token table to give byte-long calls full 32-bit reach while dramatically reducing code size. The article includes rationale, tradeoffs, a simple proof-of-concept x86 interpreter, and the basic lookup equation for hardware implementation.
MyHDL Resources and Projects
Christopher Felton has pulled together a compact, practical guide to learning and using MyHDL, with the essential manual, Jan Decaluwe's deep dives, presentations, example projects, and active Git/Bitbucket repos. Whether you want a tutorial path, reference reads, or hands-on FPGA projects from simple LEDs to SDR and DSP cores, this curated list points you to vetted resources and real designs to study and reuse.
Two jobs
Stephane Boucher explains why EmbeddedRelated went quiet for a few months after a volunteer project demanded more of his time. He and his wife organized a clown-gymnastics show with 15 kids, sold more than 700 of 800 tickets, and raised $2,700 for the Tree of Hope. Now the shows are done and he plans to resume regular posting with new site features.
MyHDL @EDAPlayground
MyHDL just got easier to try: it's available on EDAPlayground, so you can run Python-based HDL verification directly in the browser. The two-panel editor places the testbench on the left and the HDL under test on the right, with public examples such as a simple strobe and a RAM test ready to copy. Christopher Felton also links a curated resource list to help you get started quickly.
Running Average
This post shows a lightweight running average variant that cleans up noisy wheel-encoder timing using a shift-based divide-by-8 and a small rounding constant. The filter updates as M1 = M0 + (t0 - A0), where A0 is estimated from the previous average, so each new measurement nudges the estimate rather than immediately replacing it. It trades exact oldest-sample subtraction for low resource cost and strong noise suppression.
Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
Tool install for examples
The post explains the toolchain and installs needed to compile the FPGARelated MyHDL examples. It notes that examples use MyHDL for hardware description and the myhdl_tools/rhea.build Python packages to drive the FPGA vendor tools, so the full flow runs from a Python environment. The author lists required installs: MyHDL (pip or GitHub), myhdl_tools (Bitbucket), the rhea.build automation package, and the FPGA vendor toolchains (Xilinx ISE WebPACK, Altera Quartus, Lattice Diamond). Board-specific programming utilities such as fpgalink and xstools are also required for various development boards. Most examples live in a Bitbucket repository or gist and include a test_and_build_.py script that automates convert, synthesize, map, place-and-route, and bitfile generation. A 2015 changelog notes some tools were deprecated and repository locations were updated.
VGA Output in 7 Slices. Really.
Victor Yurkovsky shows how to generate VGA timing on a Xilinx Spartan3 using clever SRL16 tricks to squeeze the generator into just a few slices. By using 32-bit SRLs for line pulses, two mutually prime SRL lengths as a divide-by-99 timebase, and tapped SRLs to combine HSYNC and HBLANK, the approach achieves accurate-enough horizontal and vertical timing with minimal LUT usage.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
Homebrew CPUs: Color Languages
Victor Yurkovsky proposes turning color from mere syntax highlighting into a semantic tool for a Forth-like CPU, letting color pick which stack an operation touches. He outlines a "Rainbow Forth" where green and blue select two datastacks, red denotes the return stack, gray means use the caller's color, and white is neutral. The post sketches CPU changes, a COLOR register, call encoding and immediate-mode coloring, and teases editor and compiler implications for implementing this idea on a J1-style core.
Windows XP and Win32 - the Platform of the Future!
Victor Yurkovsky makes the contrarian case that an offline Windows XP VM running Win32 is the most practical platform for modern FPGA development. He explains how Xilinx ISE and related tools often behave far better under XP than on modern Linux distributions, and how VirtualBox fixes USB and GUI headaches. If you maintain FPGA toolchains or write compact C/C++ utilities, this retro setup can save time and frustration.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Little to no benefit from C based HLS
Christopher shows why C-based HLS delivers little practical benefit compared with a MyHDL RTL approach, using a Vivado HLS median-filter example. He walks through the sort-network median, compares C and MyHDL implementations, and argues MyHDL is as concise while providing clearer microarchitecture control. The post emphasizes that choosing the right algorithm is the hard part, and HLS won’t replace hardware understanding.
Designing Embedded System with FPGA - 1
Getting an embedded system running on an FPGA is much simpler than it sounds when you use Xilinx EDK and a soft processor. Pragnesh Patel walks through a beginner-friendly approach using the MicroBlaze CPU, drag-and-drop IP cores, and a Spartan-3E starter kit so you can assemble peripherals without deep VHDL knowledge. The post focuses on the EDK base system builder and first setup steps to generate a working design.
Mastering Modern FPGA Skills for Engineers
In the rapidly evolving tech industry, engineers must acquire proficiency in modern FPGA skills. These skills empower engineers to optimize designs, minimize resource usage, and efficiently address FPGA design challenges while ensuring functionality, security, and compliance.
Mathematics and Cryptography
Cryptographic math can look intimidating, but this roundup trims it to what FPGA engineers actually need. It groups concise articles on number theory and elliptic curves, focusing on polynomial math over Galois fields, FPGA-friendly inversion and one-clock-cycle techniques, and elliptic-curve key exchange and digital signatures. Read this to learn which subroutines to implement first and how to turn math into Verilog or VHDL.
FPGA skills for the modern world
FPGA demand is booming across industries from automotive to edge AI, and employers want engineers who can think in hardware. This post explains the mindset shift to RTL-level, concurrent design, waveform-based debugging with ILAs, and modern verification flows. It also highlights the practical skills that make you marketable, including HDLs, SoC/Linux integration, RISC-V know-how, and high-speed design techniques.
Introducing the VPCIe framework
Simulating an embedded CPU and FPGA together is painful when PCI Express is in the middle, so Fabien Le Mentec built VPCIe to virtualize that link. VPCIe traps PCIe accesses from a QEMU-hosted CPU and forwards them to a GHDL-driven VHDL simulation using TCP, letting you run unmodified Linux and drivers against your hardware model. The project is open source on GitHub and supports remote or concurrent device simulations.
Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed
Built around modest FPGA hardware, this post presents a practical test-bed for evaluating high-speed, low-latency feedback controllers. It covers ADC/DAC specifications, basic and arbitrary test signals, and an IFFT-based generator that can produce thousands of simultaneous tones for rapid Bode, phase, and latency measurements. The article also compares two IFFT strategies, explains turbo sampling, and shows open- and closed-loop test configurations.
Tools of the Trade: reading PDFs (and keeping bookmarks)
Victor Yurkovsky recommends MuPDF as a fast, no-frills PDF viewer and shares a tiny C tweak that makes bookmarks persistent and portable. The mod writes a 40-byte file next to each PDF containing ten 4-byte page numbers, so bookmarks follow your files across machines. If you juggle dozens of datasheets and manuals, this keyboard-driven workflow makes reading and navigation dramatically less painful.
Windows XP and Win32 - the Platform of the Future!
Victor Yurkovsky makes the contrarian case that an offline Windows XP VM running Win32 is the most practical platform for modern FPGA development. He explains how Xilinx ISE and related tools often behave far better under XP than on modern Linux distributions, and how VirtualBox fixes USB and GUI headaches. If you maintain FPGA toolchains or write compact C/C++ utilities, this retro setup can save time and frustration.
Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA
Sriyash Caculo is building a bridge between filter design and hardware by implementing digital filter blocks in MyHDL and integrating them with PyFDA as part of a Google Summer of Code project. The work aims to convert PyFDA floating point designs into fixed point MyHDL blocks that automatically generate VHDL or Verilog, with tests and tutorials to ensure correctness and usability.
One Clock Cycle Polynomial Math
Error correction codes and cryptographic computations are most easily performed working with GF(2^n)
