Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
MyHDL FPGA Tutorial I (LED Strobe)
Skip Verilog and try MyHDL, a Python-based HDL, to build and simulate an FPGA LED strobe in this hands-on tutorial. Christopher Felton walks through a parameterized LED shifter, py.test driven verification, and automated conversion to Verilog and bitstreams for several development boards. The post includes scripts to generate pin constraints and run vendor tools so you can build and program boards from one language.
Oscilloscope Dreams
Jason Sachs walks through practical oscilloscope buying criteria for embedded engineers, focusing on bandwidth, channel count, hi-res acquisition, and probing. He explains why mixed-signal scopes and hi-res mode matter, when a 100 MHz scope is sufficient and when to keep a higher-bandwidth instrument, and how probe grounding and waveform export can ruin measurements. Real-world brand notes and try-before-you-buy advice round out the guidance.
FPGA or DSP Processor - Parameters to Make the Right Choice
Muhammad Yasir breaks down the practical tradeoffs between FPGAs and DSP processors for real-world signal-processing systems. He offers concrete rules of thumb on sampling-rate and data-rate limits, MMAC performance bands, and when conditional logic or floating-point favors a DSP. The post also covers power, form factor, maintainability, and development-time tradeoffs to help architects pick the right platform.
Using GHDL for interactive simulation under Linux
Martin walks through using the free GHDL VHDL simulator on Linux to go beyond static testbenches and run interactive simulations. You will see how GHDL and gtkwave give a fast, low-cost waveform workflow, how to call C code from VHDL via the VHPI interface, and how simple pipes let real software talk to your simulated FPGA for deeper system-level debugging.
VHDL tutorial - A practical example - part 3 - VHDL testbench
Gene Breniman walks a complete VHDL testbench workflow for a CPLD-based data acquisition engine, from Xilinx ISE testbench generation to stimulus processes. He shows clock and SPI gating, a simulated ADC data generator tied to ADC_LRCK and ADC_BCK, and how simulation revealed a timing bug in the nvSRAM header that was then fixed in the VHDL. Practical and hands-on for verification work.
Verilog vs VHDL
Muhammad Yasir compares Verilog and VHDL by tracing their history, core features, and global usage to help engineers pick an HDL. The post explains where each language shines: Verilog for concise, low-level IC modeling and faster coding, VHDL for strong typing, packages, and system-level clarity, and it uses Google Trends and market examples to put adoption into context.
VHDL tutorial - A practical example - part 2 - VHDL coding
Gene Breniman walks through the VHDL coding for a CPLD-based data acquisition engine, turning the hardware spec into a working state machine and signal generators. The article explains SPI and I2S timing choices, an internal SPI peripheral latch, and counter-based timing (seqCount and CycleCnt) used to create LRCK, BCK, SPI SCK and nvSRAM write control. It’s a practical, implementation-focused guide for embedded designers.
USB-FPGA : Introduction
Christopher Felton recounts a six-year hobby project to build an open-source USB-FPGA board and its toolchain, from PCB to gateware, firmware, and PC software. He explains why the Cypress FX2 and a Spartan3 were chosen, how the USBP framework supported multiple boards, and why the project’s open-source ambitions didn’t attract the collaboration he expected. Expect practical design and community lessons.
StrangeCPU #4. Microcode
Victor Yurkovsky shows how a sliding-window opcode scheme turns tiny 8–9 bit tokens into wide microinstructions on an FPGA, letting you pack rich behavior into compact code. The post explains visibility ranges, instruction-data representation, and a low-cost way to add a Red-program counter so runs of microcode execute efficiently with minimal hardware overhead.
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Victor Yurkovsky extends his sliding-window token machine idea to instruction decoding, showing how 8/9-bit tokens can index shared "Blue" memory as 32-bit literals, call targets, or decoded instructions. The approach makes instructions dynamic entries that slide with the window, enabling rare opcodes to be synthesized on demand and reducing fixed opcode bloat. He also covers the 0-bit window (the stack), FPGA BRAM tagging, and the latency trade-offs.
Designing Embedded Systems with FPGA-2
Turning an FPGA hardware design into a running embedded system is mostly tool work. This post walks through using Xilinx EDK to compile a base design into a .bit bitstream, generate libraries and board support packages from .mhs and .mss files, and build MicroBlaze applications with GCC. It highlights the default boot placement at 0x0 and why some apps need an explicit execution transfer.
Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
Yet another PWM
The provided record for Anton Babushkin’s post “Yet another PWM” contains no article body, so the actual technical content is not available for review. The title and site context indicate the post concerns pulse-width modulation (PWM), but specific implementation details, language, or examples cannot be confirmed from the supplied input. This metadata therefore documents the absence of content, recommends steps to recover the original post, and flags that any downstream use (tagging, excerpts, or code extraction) must wait until the full text is retrieved from FPGARelated’s archive or the author’s copy to avoid misrepresentation.
MyHDL Resources and Projects
Christopher Felton has pulled together a compact, practical guide to learning and using MyHDL, with the essential manual, Jan Decaluwe's deep dives, presentations, example projects, and active Git/Bitbucket repos. Whether you want a tutorial path, reference reads, or hands-on FPGA projects from simple LEDs to SDR and DSP cores, this curated list points you to vetted resources and real designs to study and reuse.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
Introduction to FPGA Technology
Muhammad Yasir lays out a concise primer on FPGA fundamentals, covering internal architecture, vendors, and practical selection criteria. He explains how logic cells, LUTs, flip-flops, carry chains, block RAM, and I/O blocks combine to determine capacity and performance. This friendly overview shows why FPGAs beat ASICs for low-volume or rapidly changing designs, and how to match device resources to your application needs.
Summer of gateware is coming (again)
Wondering what gateware will come out of this summer? Christopher Felton announces MyHDL is back in Google Summer of Code and has been awarded six student slots. Projects span GEMAC, a Leros tiny processor, JPEG encoder front/backends, RISC-V tooling and HDMI+RISC-V work. Follow along for short project updates and a final summer summary.
PicoBlaze - Program RAM Access for an Interactive Monitor
You can give PicoBlaze a live interactive monitor without reconfiguring the FPGA. Victor Yurkovsky walks through using the BRAM's unused port by replacing the assembler template with a dual-ported RAMB16_S18_S18 and exposing maddr, mfromram, mtoram and mwr ports. The post includes IO decoding and a PicoBlaze assembly test to read, write and increment program memory over a serial link.
USB-FPGA : Introduction
Christopher Felton recounts a six-year hobby project to build an open-source USB-FPGA board and its toolchain, from PCB to gateware, firmware, and PC software. He explains why the Cypress FX2 and a Spartan3 were chosen, how the USBP framework supported multiple boards, and why the project’s open-source ambitions didn’t attract the collaboration he expected. Expect practical design and community lessons.
FPGA Bloggers Needed - New Reward System
You can earn up to $500 for a single FPGA blog post on FPGARelated. Stephane Boucher announces a new pageview-based reward system that pays $25 for every 250 unique pageviews, capped at $500 when a post reaches 5,000 views. If you write about Verilog, VHDL, or FPGA design and want to share expertise while getting paid, fill the short application form to apply.
Designing Embedded Systems with FPGA-2
Turning an FPGA hardware design into a running embedded system is mostly tool work. This post walks through using Xilinx EDK to compile a base design into a .bit bitstream, generate libraries and board support packages from .mhs and .mss files, and build MicroBlaze applications with GCC. It highlights the default boot placement at 0x0 and why some apps need an explicit execution transfer.
Elliptic Curve Digital Signatures
Elliptic curve digital signatures deliver compact, strong message authentication by combining a hash of the message with elliptic curve point math. This post walks through the standard sign and verify equations, showing why recomputing a point R' yields the same x coordinate only when the hash matches. It also explains the Nyberg-Rueppel alternative that removes modular inversion and an FPGA-friendly trick of transmitting point D to avoid integer modular arithmetic.
Yet another PWM
The provided record for Anton Babushkin’s post “Yet another PWM” contains no article body, so the actual technical content is not available for review. The title and site context indicate the post concerns pulse-width modulation (PWM), but specific implementation details, language, or examples cannot be confirmed from the supplied input. This metadata therefore documents the absence of content, recommends steps to recover the original post, and flags that any downstream use (tagging, excerpts, or code extraction) must wait until the full text is retrieved from FPGARelated’s archive or the author’s copy to avoid misrepresentation.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
Tool install for examples
The post explains the toolchain and installs needed to compile the FPGARelated MyHDL examples. It notes that examples use MyHDL for hardware description and the myhdl_tools/rhea.build Python packages to drive the FPGA vendor tools, so the full flow runs from a Python environment. The author lists required installs: MyHDL (pip or GitHub), myhdl_tools (Bitbucket), the rhea.build automation package, and the FPGA vendor toolchains (Xilinx ISE WebPACK, Altera Quartus, Lattice Diamond). Board-specific programming utilities such as fpgalink and xstools are also required for various development boards. Most examples live in a Bitbucket repository or gist and include a test_and_build_.py script that automates convert, synthesize, map, place-and-route, and bitfile generation. A 2015 changelog notes some tools were deprecated and repository locations were updated.
