VHDL tutorial - Creating a hierarchical design
In earlier blog entries I introduced some of the basic VHDL concepts. First, developing a function ('VHDL tutorial') and later verifying and refining it ('VHDL tutorial - part 2 - Testbench' and 'VHDL tutorial - combining clocked and sequential logic'). In this entry I will describe how to...
VHDL tutorial - combining clocked and sequential logic
In an earlier article on VHDL programming ("VHDL tutorial" and "VHDL tutorial - part 2 - Testbench", I described a design for providing a programmable clock divider for a ADC sequencer. In this example, I showed how to generate a clock signal (ADCClk), that was to be programmable over a series of fixed rates (20MHz, 10MHz, 4MHz, 2MHz, 1MHz and 400KHz), given a master clock rate of 40MHz. A reader of that article had written to ask if it was possible to extend the design to...
Designing Embedded Systems with FPGA-2
In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream andstored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and...
VHDL tutorial - part 2 - Testbench
In an earlier article I walked through the VHDL coding of a simple design. In this article I will continue the process and create a test bench module to test the earlier design. The Xilinx ISE environment makes it pretty easy to start the testing process. To start the process, select "New Source" from the menu items under "Project". This launches the "New Source Wizard". From within the Wizard select "VHDL Test Bench" and enter the name of the new module (click 'Next' to...
Designing Embedded System with FPGA - 1
With the introduction of soft processors and related tools (like EDK from Xilinx), implementation of basic embedded system in FPGA is made easy. This requires very little or almost no knowledge of VHDL programming. Actually that’s how I started. If user is interested in taking full advantage of FPGA and its parallel processing power, then yes, detail understanding of soft processor, its peripheral bus and VHDL programming is required.
I will start with...
VHDL tutorial
When I was first introduced to "Programmable Logic" several years ago, it was an answer to many of the challenges that I was struggling with. Though the parts were primitive by today's standards (simple PALs verses FPGA), they were an extremely cost effective tool addressing the need for specialized logic blocks.
I have continued to incorporate these powerful blocks into many of my latest designs. My current favorite part line is the Xilinx CoolRunner series (XC2Cxxx). In this...
New Discussion Group: DSP & FPGA
I have just created a new discussion group for engineers implementing DSP functions on FPGAs. The creation of this group has been on my todo list for a long time. If you want to join the group, send a blank email to: fpgadsp-subscribe@yahoogroups.com
As usual, it should take a few weeks before there are enough members for interesting discussions to get started.
Holy Bit Bucket
Was my first response after reading some of the recent news on Tabula. If you Google "Tabula FPGA" you will find a link to the company and a bunch of recent articles. The company appears to be building buzz (hmmm, wonder if they have facebook and twitter accounts) about their technology and future products.
There has been some discussions (comp.arch.fpga) and a bunch of small articles about the relatively new FPGA company. The company is trying to increase...
Grandiose Delusions
Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools. In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL. For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.
Many design languages have relied on that first big...
My VHDL <= monpjc; Journey
I always like to start my first blog on a website with a bit of a introduction as to who I am and what I’ll be writting about. I feel this gives you the reader a opportunity to see where I’m coming from and understand a little of my point of view. So when I was asked to come and start blogging on FPGARelated I wondered what I should say. So for my first blog its all about how me, aka monpjc, and how I got into VHDL.
It started a long time ago when I was working for a...
What do Ohio, Python, and FPGAs have in common?
Anyone in the Columbus Ohio area in the United States this upcoming weekend (7/27 and 7/28) should stop by the @pyohio conference. This is a *FREE* regional python conference. I will be giving a talk at the end of the day Sunday, discussing MyHDL, FPGAs, and a hands-on workshop following the presentation.
The talk will focus on introducing programmable hardware to "imperative thinkers". Anyone curious about FPGAs, Python, or familiar with FPGAs or embedded...
MyHDL Presentation Examples
The last two years I presented at EELive. The first year as an overview of MyHDL and a strong case why you should be using MyHDL as your hardware description language (HDL) [paper]. The second year was an introduction to three alternative HDLs (alt.hdl), including MyHDL. I also presented at a regional Python conferene: pyohio. At the Python conference I presented...
MyHDL ... MyPWM
The PWM topic appears to be popular lately on the fpgarelated site. This is coincidence, but I typically find the topic of modulating and demodulating signals interesting. For digital systems it is always entertaining to play with PWMs. The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin. The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).
As...
Tool install for examples
Most of my examples on fpgarelated use MyHDL for the hardware description and another Python package myhdl_tools rhea.build to control the FPGA vendor's software. This means everything is controlled and run from the Python environment.
Install the following to compile the posted examples:
MyHDL package : pip myhdl or myhdl github myhdl_tools : myhdl_tools bitbucket rhea...Summer of Gateware
This (last) summer the MyHDL project participated in the Google Summer of Code (GSoC) as a sub-organization under the Python Software Foundation (PSF). This was our first year participating - there was a lot for us to learn. Overall it was a worthwhile and beneficial activity.
Being a first time sub-org we were limited to a maximum of two students. We had nine students apply and twelve mentors volunteer. Only being able to select two students...
MyHDL Presentation Examples
The last two years I presented at EELive. The first year as an overview of MyHDL and a strong case why you should be using MyHDL as your hardware description language (HDL) [paper]. The second year was an introduction to three alternative HDLs (alt.hdl), including MyHDL. I also presented at a regional Python conferene: pyohio. At the Python conference I presented...
New Design - Finally!
For those of you who are familiar with my work, you already know that FPGARelated.com is not the only engineering web site that I publish. I also publish DSPRelated.com and EmbeddedRelated.com. Those two web sites have been on a new design for quite some time now and porting the new design to FPGARelated.com has been on my todo list for too long! I am glad today to announce that I have finally found the time to apply the more modern design to FPGARelated.com.
Thank you...
MyHDL @EDAPlayground
Trying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL.
The @EDAPlayground has two main panels. On the left is the testbench and the right the HDL description to be tested.
There are a couple examples...
My VHDL <= monpjc; Journey
I always like to start my first blog on a website with a bit of a introduction as to who I am and what I’ll be writting about. I feel this gives you the reader a opportunity to see where I’m coming from and understand a little of my point of view. So when I was asked to come and start blogging on FPGARelated I wondered what I should say. So for my first blog its all about how me, aka monpjc, and how I got into VHDL.
It started a long time ago when I was working for a...
A Bit Bucket had Holes
Couple months ago I wrote a quick little blog about a company called Tabula. Tabula has a virtual 3D approach to achieving higher logic density in an FPGA. See the previous blog for more information.
Along similar lines was another company called TierLogic which actually had multiple physical layers. I was impressed with the Tabula approach and claims. Along the same lines the TierLogic technology looked promising as well. But, EE Times has reported that...
Holy Bit Bucket
Was my first response after reading some of the recent news on Tabula. If you Google "Tabula FPGA" you will find a link to the company and a bunch of recent articles. The company appears to be building buzz (hmmm, wonder if they have facebook and twitter accounts) about their technology and future products.
There has been some discussions (comp.arch.fpga) and a bunch of small articles about the relatively new FPGA company. The company is trying to increase...
