BGA and QFP at Home 1 - A Practical Guide.
It's a myth that BGAs and fine-pitch QFPs can't be soldered at home. Victor Yurkovsky lays out a practical, no-frills approach for hobbyists to design and assemble FPGA boards using 2-layer PCBs, breakout modules, and low-cost reflow methods like toaster ovens or hotplates. The article focuses on manufacturable PCB choices, netlist-driven workflows, and power/decoupling tactics that make high-density parts approachable for amateurs.
PicoBlaze - Program RAM Access for an Interactive Monitor
You can give PicoBlaze a live interactive monitor without reconfiguring the FPGA. Victor Yurkovsky walks through using the BRAM's unused port by replacing the assembler template with a dual-ported RAMB16_S18_S18 and exposing maddr, mfromram, mtoram and mwr ports. The post includes IO decoding and a PicoBlaze assembly test to read, write and increment program memory over a serial link.
MyHDL ... MyPWM
Christopher Felton presents a compact MyHDL PWM engine designed to be configured at design time and targeted for FPGA synthesis. The module derives PWM bit width from the system clock frequency and desired pwm_frequency, truncates inputs when necessary, and prints parameter summaries for different clock/pwm combinations. The post includes the full MyHDL source and a simulation waveform showing the input signal and the modulated output, making it easy to reproduce.
VGA Output in 7 Slices. Really.
Victor Yurkovsky shows how to generate VGA timing on a Xilinx Spartan3 using clever SRL16 tricks to squeeze the generator into just a few slices. By using 32-bit SRLs for line pulses, two mutually prime SRL lengths as a divide-by-99 timebase, and tapped SRLs to combine HSYNC and HBLANK, the approach achieves accurate-enough horizontal and vertical timing with minimal LUT usage.
How to start in FPGA development? - Simulation software tools
Nuria Orduna lays out a pragmatic approach to FPGA simulation, comparing Xilinx ISE with integrated ModelSim against a three-tool flow with ModelSim and Precision. She explains why independent ModelSim runs and using notepad++ for VHDL can speed debugging, and why Precision and CoreGen conversions can be painful. Read for a compact, practiced workflow to simplify simulation, synthesis, and project organization.
How to start in FPGA development? - Some tips
Starting from zero, this practical primer walks new FPGA users through the early decisions and habits that make projects work. Nuria Orduna covers how to pick a device, sketch a clear dataflow, prototype in MATLAB or C, organize VHDL entities versus functions, and use ModelSim .do files and testbenches to debug before programming the board. Read it for concise, hands-on starting points.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
An Editor for HDLs
If you prefer Notepad++ over Emacs, Dave Vandenbout shows how to turn it into a capable HDL editor using templates, a Perl package generator, and Emacs run in batch mode for beautification. He covers FingerText snippets for VHDL skeletons, binding a Perl script to auto-create/update package component declarations, and invoking Emacs from a hotkey to format files with one keystroke.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
Use Microprogramming to Save Resources and Increase Functionality
Microprogramming can rescue an overfull FPGA, Michael Morris shows, by compressing control logic and time-multiplexing FIFO storage. He replaces an ABEL state machine with a small microprogram ROM that uses block RAM for deep Rx/Tx FIFOs and LUT RAM for pointers and counters, freeing about 25 percent of the device. The article includes Verilog comparisons, resource tables, and a microassembler link to reproduce the approach.
VGA Output in 7 Slices. Really.
Victor Yurkovsky shows how to generate VGA timing on a Xilinx Spartan3 using clever SRL16 tricks to squeeze the generator into just a few slices. By using 32-bit SRLs for line pulses, two mutually prime SRL lengths as a divide-by-99 timebase, and tapped SRLs to combine HSYNC and HBLANK, the approach achieves accurate-enough horizontal and vertical timing with minimal LUT usage.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
Tools of the Trade: reading PDFs (and keeping bookmarks)
Victor Yurkovsky recommends MuPDF as a fast, no-frills PDF viewer and shares a tiny C tweak that makes bookmarks persistent and portable. The mod writes a 40-byte file next to each PDF containing ten 4-byte page numbers, so bookmarks follow your files across machines. If you juggle dozens of datasheets and manuals, this keyboard-driven workflow makes reading and navigation dramatically less painful.
PicoBlaze - Program RAM Access for an Interactive Monitor
You can give PicoBlaze a live interactive monitor without reconfiguring the FPGA. Victor Yurkovsky walks through using the BRAM's unused port by replacing the assembler template with a dual-ported RAMB16_S18_S18 and exposing maddr, mfromram, mtoram and mwr ports. The post includes IO decoding and a PicoBlaze assembly test to read, write and increment program memory over a serial link.
How to start in FPGA development? - Simulation software tools
Nuria Orduna lays out a pragmatic approach to FPGA simulation, comparing Xilinx ISE with integrated ModelSim against a three-tool flow with ModelSim and Precision. She explains why independent ModelSim runs and using notepad++ for VHDL can speed debugging, and why Precision and CoreGen conversions can be painful. Read for a compact, practiced workflow to simplify simulation, synthesis, and project organization.
How to start in FPGA development? - Some tips
Starting from zero, this practical primer walks new FPGA users through the early decisions and habits that make projects work. Nuria Orduna covers how to pick a device, sketch a clear dataflow, prototype in MATLAB or C, organize VHDL entities versus functions, and use ModelSim .do files and testbenches to debug before programming the board. Read it for concise, hands-on starting points.
MyHDL ... MyPWM
Christopher Felton presents a compact MyHDL PWM engine designed to be configured at design time and targeted for FPGA synthesis. The module derives PWM bit width from the system clock frequency and desired pwm_frequency, truncates inputs when necessary, and prints parameter summaries for different clock/pwm combinations. The post includes the full MyHDL source and a simulation waveform showing the input signal and the modulated output, making it easy to reproduce.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
How to start in FPGA development? - Some tips
Starting from zero, this practical primer walks new FPGA users through the early decisions and habits that make projects work. Nuria Orduna covers how to pick a device, sketch a clear dataflow, prototype in MATLAB or C, organize VHDL entities versus functions, and use ModelSim .do files and testbenches to debug before programming the board. Read it for concise, hands-on starting points.
How to start in FPGA development? - Simulation software tools
Nuria Orduna lays out a pragmatic approach to FPGA simulation, comparing Xilinx ISE with integrated ModelSim against a three-tool flow with ModelSim and Precision. She explains why independent ModelSim runs and using notepad++ for VHDL can speed debugging, and why Precision and CoreGen conversions can be painful. Read for a compact, practiced workflow to simplify simulation, synthesis, and project organization.
Tools of the Trade: reading PDFs (and keeping bookmarks)
Victor Yurkovsky recommends MuPDF as a fast, no-frills PDF viewer and shares a tiny C tweak that makes bookmarks persistent and portable. The mod writes a 40-byte file next to each PDF containing ten 4-byte page numbers, so bookmarks follow your files across machines. If you juggle dozens of datasheets and manuals, this keyboard-driven workflow makes reading and navigation dramatically less painful.
One Clock Cycle Polynomial Math
Error correction codes and cryptographic computations are most easily performed working with GF(2^n)
Polynomial Inverse
One of the important steps of computing point addition over elliptic curves is a division of two polynomials.
PicoBlaze - Program RAM Access for an Interactive Monitor
You can give PicoBlaze a live interactive monitor without reconfiguring the FPGA. Victor Yurkovsky walks through using the BRAM's unused port by replacing the assembler template with a dual-ported RAMB16_S18_S18 and exposing maddr, mfromram, mtoram and mwr ports. The post includes IO decoding and a PicoBlaze assembly test to read, write and increment program memory over a serial link.
MyHDL Interface Example
Christopher Felton shows how MyHDL 0.9 interfaces bundle Signals into a single bus object to cut connector clutter and simplify module connections. The post walks through a pedagogical example where button presses drive a memory-mapped BareBoneBus read-modify-write that inverts LEDs, with a TDD-style testbench and notes on converting to Verilog/VHDL and loading the example on supported boards.
MyHDL ... MyPWM
Christopher Felton presents a compact MyHDL PWM engine designed to be configured at design time and targeted for FPGA synthesis. The module derives PWM bit width from the system clock frequency and desired pwm_frequency, truncates inputs when necessary, and prints parameter summaries for different clock/pwm combinations. The post includes the full MyHDL source and a simulation waveform showing the input signal and the modulated output, making it easy to reproduce.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
