Using GHDL for interactive simulation under Linux
Martin walks through using the free GHDL VHDL simulator on Linux to go beyond static testbenches and run interactive simulations. You will see how GHDL and gtkwave give a fast, low-cost waveform workflow, how to call C code from VHDL via the VHPI interface, and how simple pipes let real software talk to your simulated FPGA for deeper system-level debugging.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
Are you kidding me?
Christopher Felton pushes back on the idea that C/C++/SystemC are the natural path to higher-abstraction FPGA design. He argues hardware designers often do not use C-family languages for modeling and simulation, so choosing C as the HLS lingua franca may be more about tool momentum than suitability. The post urges reconsidering languages with higher abstraction and lower cost of entry for system modeling and HLS.
MyHDL @EDAPlayground
MyHDL just got easier to try: it's available on EDAPlayground, so you can run Python-based HDL verification directly in the browser. The two-panel editor places the testbench on the left and the HDL under test on the right, with public examples such as a simple strobe and a RAM test ready to copy. Christopher Felton also links a curated resource list to help you get started quickly.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
