MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
An Editor for HDLs
If you prefer Notepad++ over Emacs, Dave Vandenbout shows how to turn it into a capable HDL editor using templates, a Perl package generator, and Emacs run in batch mode for beautification. He covers FingerText snippets for VHDL skeletons, binding a Perl script to auto-create/update package component declarations, and invoking Emacs from a hotkey to format files with one keystroke.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
MyHDL Interface Example
Christopher Felton shows how MyHDL 0.9 interfaces bundle Signals into a single bus object to cut connector clutter and simplify module connections. The post walks through a pedagogical example where button presses drive a memory-mapped BareBoneBus read-modify-write that inverts LEDs, with a TDD-style testbench and notes on converting to Verilog/VHDL and loading the example on supported boards.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
Makefiles for Xilinx Tools
Building a bitstream from HDL is messy, and Victor Yurkovsky lays out a minimal, practical makefile workflow for Xilinx ISE and XST. He shows a simple project layout, techniques to tame ISE's generated logs and temps, and a ready-to-clone repo; an LED blinker example builds to bitstream in under 20 seconds on his machine. Use it as a pragmatic starting point for command-line FPGA builds.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
MyHDL Interface Example
Christopher Felton shows how MyHDL 0.9 interfaces bundle Signals into a single bus object to cut connector clutter and simplify module connections. The post walks through a pedagogical example where button presses drive a memory-mapped BareBoneBus read-modify-write that inverts LEDs, with a TDD-style testbench and notes on converting to Verilog/VHDL and loading the example on supported boards.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
