Polynomial Math
This post walks through squaring and inversion in a tiny finite field to make ECC math tangible. Using GF(2^5) with primitive polynomial beta^5 + beta^2 + 1 it shows why squaring cancels cross terms so you only need half the lookup table, and how Fermat exponentiation computes inverses via repeated squarings and multiplies. It also demonstrates the Extended Euclid polynomial inverse and compares FPGA and CPU tradeoffs.
Welcoming MANY New Bloggers!
A big influx of new voices just joined DSPRelated, and Stephane Boucher introduces the growing roster of contributors and their backgrounds. The post lists dozens of newly approved bloggers, highlights the range of DSP and embedded expertise they bring, and asks readers to leave constructive feedback on posts. It also explains why some applicants may not have been accepted yet and how to apply properly.
Recruiting New Bloggers!
EmbeddedRelated is expanding its blogging team, and Stephane Boucher is inviting engineers, students, hobbyists, and researchers to contribute. He points to the success of earlier contributors and says the community has already read their articles more than 1,250,000 times. If you have knowledge to share, this post explains how to pitch a topic and get started.
Summer of Gateware
Christopher Felton walks through MyHDL's first year as a Google Summer of Code sub organization, from selecting two students to shipping SDRAM and conversion work. He highlights the practical bumps, including proposal expectations, the value of early patches, and the need for frequent mentoring and flexible milestones. The post shares concrete lessons for mentors, students, and projects planning to participate in GSoC.
Tools of the Trade: reading PDFs (and keeping bookmarks)
Victor Yurkovsky recommends MuPDF as a fast, no-frills PDF viewer and shares a tiny C tweak that makes bookmarks persistent and portable. The mod writes a 40-byte file next to each PDF containing ten 4-byte page numbers, so bookmarks follow your files across machines. If you juggle dozens of datasheets and manuals, this keyboard-driven workflow makes reading and navigation dramatically less painful.
Inside the Spartan-6: Using LUTs to optimize circuits
Victor Yurkovsky hit poor synthesis packing while building a J1 CPU on Spartan-6 and traced the problem to an 18-bit logic ALU that mapped to many slices. He demonstrates a practical fix: instantiate LUT6 primitives with carefully chosen INIT values, then use RLOC placement to stack the per-bit LUTs and collapse the design down to five slices. This is a hands-on guide to Xilinx-specific optimization when synthesis falls short.
Homebrew CPUs: Color Languages
Victor Yurkovsky proposes turning color from mere syntax highlighting into a semantic tool for a Forth-like CPU, letting color pick which stack an operation touches. He outlines a "Rainbow Forth" where green and blue select two datastacks, red denotes the return stack, gray means use the caller's color, and white is neutral. The post sketches CPU changes, a COLOR register, call encoding and immediate-mode coloring, and teases editor and compiler implications for implementing this idea on a J1-style core.
Homebrew CPUs: Messing around with a J1
Victor Yurkovsky takes James Bowman's compact J1 stack CPU and starts hacking: he trims the ALU, replaces the barrel shifter with simpler shifts, and experiments with dual stacks and memory/IO feeding directly into the ALU. The article walks through small, practical changes that cut logic, add instructions, and boost timing on Spartan-6. It's a hands-on tour that shows how approachable homebrew CPUs can be.
Makefiles for Xilinx Tools
Building a bitstream from HDL is messy, and Victor Yurkovsky lays out a minimal, practical makefile workflow for Xilinx ISE and XST. He shows a simple project layout, techniques to tame ISE's generated logs and temps, and a ready-to-clone repo; an LED blinker example builds to bitstream in under 20 seconds on his machine. Use it as a pragmatic starting point for command-line FPGA builds.
Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines
The article presents a synthesizable Verilog microprogram controller (MPC) modeled on the Fairchild F9408 that simplifies development of complex microprogrammed state machines. It explains desirable MPC features — a loadable program counter for sequential and non-sequential execution, conditional and multi-way branching, and a microsubroutine stack — and then provides a working HDL implementation (F9408A_MPC). The module is parameterized for microprogram address width, supports a 4-level LIFO return stack, 8-way multiway branch via an external selector, pipelined or non-pipelined operation, and registered test inputs for conditional branches. The article includes the full Verilog source and discusses practical uses of the MPC in designs from protocol controllers to a 65C02 microprocessor reimplementation.
3 Good News
Stephane Boucher reports three quick wins for the EmbeddedRelated community: two sponsors have seeded a $1,000 rewards pool, the site now serves all pages over HTTPS, and the new forums have their first active discussions. If you want a share of the sponsor-funded rewards, jump into the forums and check the Vendors Directory for opportunities. Stay tuned for more updates.
Homebrew CPUs: Messing around with a J1
Victor Yurkovsky takes James Bowman's compact J1 stack CPU and starts hacking: he trims the ALU, replaces the barrel shifter with simpler shifts, and experiments with dual stacks and memory/IO feeding directly into the ALU. The article walks through small, practical changes that cut logic, add instructions, and boost timing on Spartan-6. It's a hands-on tour that shows how approachable homebrew CPUs can be.
Polynomial Inverse
One of the important steps of computing point addition over elliptic curves is a division of two polynomials.
Use Microprogramming to Save Resources and Increase Functionality
Microprogramming can rescue an overfull FPGA, Michael Morris shows, by compressing control logic and time-multiplexing FIFO storage. He replaces an ABEL state machine with a small microprogram ROM that uses block RAM for deep Rx/Tx FIFOs and LUT RAM for pointers and counters, freeing about 25 percent of the device. The article includes Verilog comparisons, resource tables, and a microassembler link to reproduce the approach.
Elliptic Curve Cryptography - Security Considerations
The security of elliptic curve cryptography is determined by the elliptic curve discrete log problem. This article explains what that means. A comparison with real number logarithm and modular arithmetic gives context for why it is called a log problem.
BGA and QFP at Home 1 - A Practical Guide.
It's a myth that BGAs and fine-pitch QFPs can't be soldered at home. Victor Yurkovsky lays out a practical, no-frills approach for hobbyists to design and assemble FPGA boards using 2-layer PCBs, breakout modules, and low-cost reflow methods like toaster ovens or hotplates. The article focuses on manufacturable PCB choices, netlist-driven workflows, and power/decoupling tactics that make high-density parts approachable for amateurs.
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption.
One Clock Cycle Polynomial Math
Error correction codes and cryptographic computations are most easily performed working with GF(2^n)
FPGA skills for the modern world
FPGA demand is booming across industries from automotive to edge AI, and employers want engineers who can think in hardware. This post explains the mindset shift to RTL-level, concurrent design, waveform-based debugging with ILAs, and modern verification flows. It also highlights the practical skills that make you marketable, including HDLs, SoC/Linux integration, RISC-V know-how, and high-speed design techniques.
StrangeCPU #1. A new CPU
This post rethinks call instructions by factoring call targets out of every callsite and replacing them with tiny tokens. Victor Yurkovsky introduces StrangeCPU, a bytecode CPU that uses 8-bit tokens plus a static sliding-window token table to give byte-long calls full 32-bit reach while dramatically reducing code size. The article includes rationale, tradeoffs, a simple proof-of-concept x86 interpreter, and the basic lookup equation for hardware implementation.
Crowdfunding Articles?
Technical writers in the embedded world often have the expertise, but not always the time or incentive to turn it into a post. Stephane Boucher explores a crowdfunding model for technical articles, where readers would pledge small amounts to back promising abstracts before the writing begins. It is an interesting attempt to create more high quality EE content by paying authors upfront.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
Why I would choose an FPGA development board?
FPGA boards are the smarter choice for hands-on learning and flexible hardware design. Compared with microcontroller dev boards, they let you run many hardware tasks in parallel, reuse the same HDL across different vendors, and even host soft-core microcontrollers inside the fabric. This post walks through those practical advantages and points out modern low-cost boards that make FPGAs accessible for students and engineers.
Feedback Controllers - Making Hardware with Firmware. Part I. Introduction
This first post kicks off a series on using DSP and feedback control with mixed-signal electronics and FPGAs to emulate two-terminal circuits and create low latency controllers. It frames circuit emulation as a feedback problem, highlights latency as the key practical constraint, and outlines the planned evaluation hardware, target devices, and software tools that will be used in later MATLAB/Simulink and FPGA work.
What to See at Embedded World 2019
Skip the overwhelm at Embedded World 2019, Stephane Boucher lays out a practical preview of what to see and how to prioritize your time. The post helps embedded engineers focus on demos, vendor booths, and sessions that matter without getting lost on the show floor. Read it to plan a short, efficient visit that maximizes technical takeaways and networking opportunities.
Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!
Stephane Boucher is heading to Sensors Expo in San Jose for the first time, and he is bringing cameras to capture demos and build a highlights video. He is also looking for roommates for a roomy Airbnb near the convention center, plus local tips for making the most of a free day in the Bay Area. If you are attending, there is also a registration discount code and a VIP pass giveaway in the mix.
Launch of EmbeddedRelated.tv
Stephane Boucher launches EmbeddedRelated.tv to host live broadcasts from Embedded World, starting next week. The site will show a constantly evolving schedule, a Live! tab to find ongoing streams, and ad-hoc demos added from the show floor. Expect schedule conflicts and small hiccups, and plan to refresh the page and join the forum thread for real-time updates and feedback.
Elliptic Curve Cryptography - Key Exchange and Signatures
Elliptic curve mathematics over finite fields helps solve the problem of exchanging secret keys for encrypted messages as well as proving a specific person signed a particular document. This article goes over simple algorithms for key exchange and digital signature using elliptic curve mathematics. These methods are the essence of elliptic curve cryptography (ECC) used in applications such as SSH, TLS and HTTPS.
How to start in FPGA development? - Some tips
Starting from zero, this practical primer walks new FPGA users through the early decisions and habits that make projects work. Nuria Orduna covers how to pick a device, sketch a clear dataflow, prototype in MATLAB or C, organize VHDL entities versus functions, and use ModelSim .do files and testbenches to debug before programming the board. Read it for concise, hands-on starting points.
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
This installment follows the hardware from concept to first power-up for a low-latency feedback controller and arbitrary circuit emulator. It walks through the practical engineering steps, from requirements, block diagrams, and issue tracking to component selection, simulation, PCB planning, purchasing, and staged bring-up. The result is a realistic look at how careful due diligence and a few trade-offs turned a research idea into working evaluation hardware.
