Polynomial Math
This post walks through squaring and inversion in a tiny finite field to make ECC math tangible. Using GF(2^5) with primitive polynomial beta^5 + beta^2 + 1 it shows why squaring cancels cross terms so you only need half the lookup table, and how Fermat exponentiation computes inverses via repeated squarings and multiplies. It also demonstrates the Extended Euclid polynomial inverse and compares FPGA and CPU tradeoffs.
Welcoming MANY New Bloggers!
A big influx of new voices just joined DSPRelated, and Stephane Boucher introduces the growing roster of contributors and their backgrounds. The post lists dozens of newly approved bloggers, highlights the range of DSP and embedded expertise they bring, and asks readers to leave constructive feedback on posts. It also explains why some applicants may not have been accepted yet and how to apply properly.
Recruiting New Bloggers!
EmbeddedRelated is expanding its blogging team, and Stephane Boucher is inviting engineers, students, hobbyists, and researchers to contribute. He points to the success of earlier contributors and says the community has already read their articles more than 1,250,000 times. If you have knowledge to share, this post explains how to pitch a topic and get started.
Summer of Gateware
Christopher Felton walks through MyHDL's first year as a Google Summer of Code sub organization, from selecting two students to shipping SDRAM and conversion work. He highlights the practical bumps, including proposal expectations, the value of early patches, and the need for frequent mentoring and flexible milestones. The post shares concrete lessons for mentors, students, and projects planning to participate in GSoC.
Tools of the Trade: reading PDFs (and keeping bookmarks)
Victor Yurkovsky recommends MuPDF as a fast, no-frills PDF viewer and shares a tiny C tweak that makes bookmarks persistent and portable. The mod writes a 40-byte file next to each PDF containing ten 4-byte page numbers, so bookmarks follow your files across machines. If you juggle dozens of datasheets and manuals, this keyboard-driven workflow makes reading and navigation dramatically less painful.
Inside the Spartan-6: Using LUTs to optimize circuits
Victor Yurkovsky hit poor synthesis packing while building a J1 CPU on Spartan-6 and traced the problem to an 18-bit logic ALU that mapped to many slices. He demonstrates a practical fix: instantiate LUT6 primitives with carefully chosen INIT values, then use RLOC placement to stack the per-bit LUTs and collapse the design down to five slices. This is a hands-on guide to Xilinx-specific optimization when synthesis falls short.
Homebrew CPUs: Color Languages
Victor Yurkovsky proposes turning color from mere syntax highlighting into a semantic tool for a Forth-like CPU, letting color pick which stack an operation touches. He outlines a "Rainbow Forth" where green and blue select two datastacks, red denotes the return stack, gray means use the caller's color, and white is neutral. The post sketches CPU changes, a COLOR register, call encoding and immediate-mode coloring, and teases editor and compiler implications for implementing this idea on a J1-style core.
Homebrew CPUs: Messing around with a J1
Victor Yurkovsky takes James Bowman's compact J1 stack CPU and starts hacking: he trims the ALU, replaces the barrel shifter with simpler shifts, and experiments with dual stacks and memory/IO feeding directly into the ALU. The article walks through small, practical changes that cut logic, add instructions, and boost timing on Spartan-6. It's a hands-on tour that shows how approachable homebrew CPUs can be.
Makefiles for Xilinx Tools
Building a bitstream from HDL is messy, and Victor Yurkovsky lays out a minimal, practical makefile workflow for Xilinx ISE and XST. He shows a simple project layout, techniques to tame ISE's generated logs and temps, and a ready-to-clone repo; an LED blinker example builds to bitstream in under 20 seconds on his machine. Use it as a pragmatic starting point for command-line FPGA builds.
Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines
The article presents a synthesizable Verilog microprogram controller (MPC) modeled on the Fairchild F9408 that simplifies development of complex microprogrammed state machines. It explains desirable MPC features — a loadable program counter for sequential and non-sequential execution, conditional and multi-way branching, and a microsubroutine stack — and then provides a working HDL implementation (F9408A_MPC). The module is parameterized for microprogram address width, supports a 4-level LIFO return stack, 8-way multiway branch via an external selector, pipelined or non-pipelined operation, and registered test inputs for conditional branches. The article includes the full Verilog source and discusses practical uses of the MPC in designs from protocol controllers to a 65C02 microprocessor reimplementation.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
StrangeCPU #2. Sliding Window Token Machines
Victor Yurkovsky walks through a surprising CPU design that expands tiny 8/9-bit tokens into full 32-bit call targets using a sliding-window pointer table. The article explains the red/blue memory model, compilation tradeoffs like table overrun and under-run, literal factoring, FPGA scaling, and even includes an ARM Cortex-M implementation snippet to show how the interpreter works in practice.
The Spartans
Christopher Felton walks through the Spartan6 FPGA basics, explaining CLBs, slices, and the new 6-input LUTs while comparing them to Spartan3. He ran timing-driven mappings of real gateware to show practical LUT utilization differences. The post gives a pragmatic estimate of expected LUT savings and points out where mapping results can vary depending on the design.
Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines
The article presents a synthesizable Verilog microprogram controller (MPC) modeled on the Fairchild F9408 that simplifies development of complex microprogrammed state machines. It explains desirable MPC features — a loadable program counter for sequential and non-sequential execution, conditional and multi-way branching, and a microsubroutine stack — and then provides a working HDL implementation (F9408A_MPC). The module is parameterized for microprogram address width, supports a 4-level LIFO return stack, 8-way multiway branch via an external selector, pipelined or non-pipelined operation, and registered test inputs for conditional branches. The article includes the full Verilog source and discusses practical uses of the MPC in designs from protocol controllers to a 65C02 microprocessor reimplementation.
Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples
An engineer's guide to building ideal continuous-time models for hardware emulation, using TINA Spice, MATLAB and Simulink to validate controller and circuit behavior. The article shows how a passive R-C network can be emulated by an amplifier, a current measurement and a summer, with Spice, MATLAB and Simulink producing coincident Bode responses. Small phase differences between MATLAB and Simulink are noted, and sampled-data issues are slated for the next installment.
Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
This article digs into practical sampled-data issues you must address when building feedback controllers for circuit emulation. It highlights a common MATLAB versus Simulink discrepancy caused by DAC holding, explains why FOH (ramp-invariant) c2d conversion matters, and surveys latency, bit depth, filter and precision trade-offs. It also lists candidate ADCs, DACs and FPGAs used in a real evaluation platform to guide hardware choices.
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Victor Yurkovsky extends his sliding-window token machine idea to instruction decoding, showing how 8/9-bit tokens can index shared "Blue" memory as 32-bit literals, call targets, or decoded instructions. The approach makes instructions dynamic entries that slide with the window, enabling rare opcodes to be synthesized on demand and reducing fixed opcode bloat. He also covers the 0-bit window (the stack), FPGA BRAM tagging, and the latency trade-offs.
Three more things you need to know when transitioning from MCUs to FPGAs
Take a look at three more important difference between FPGAs and MCUs: "code reuse" vs templating, metastability and blocking vs. non-blocking operations.
What to See at Embedded World 2019
Skip the overwhelm at Embedded World 2019, Stephane Boucher lays out a practical preview of what to see and how to prioritize your time. The post helps embedded engineers focus on demos, vendor booths, and sessions that matter without getting lost on the show floor. Read it to plan a short, efficient visit that maximizes technical takeaways and networking opportunities.
Use Microprogramming to Save Resources and Increase Functionality
Microprogramming can rescue an overfull FPGA, Michael Morris shows, by compressing control logic and time-multiplexing FIFO storage. He replaces an ABEL state machine with a small microprogram ROM that uses block RAM for deep Rx/Tx FIFOs and LUT RAM for pointers and counters, freeing about 25 percent of the device. The article includes Verilog comparisons, resource tables, and a microassembler link to reproduce the approach.
Going back to Germany!
A conference conversation turned into a return trip to Germany for Stephane Boucher, this time to visit SEGGER’s headquarters in Dusseldorf and produce videos. The post shares how a chance introduction at ESC Boston led to the invitation, and it teases coverage from SEGGER’s 25th anniversary celebration. He also invites local tips and customer questions before the trip.
Live Streaming from Embedded World!
Stephane Boucher will bring Embedded World to engineers who cannot attend, streaming high-quality HD video from the show floor. He plans to use a professional camera and a device that bonds three internet links to keep the stream stable, and he is coordinating live sessions with vendors and select talks. Read on to learn how to vote for the presentations you want streamed.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
StrangeCPU #4. Microcode
Victor Yurkovsky shows how a sliding-window opcode scheme turns tiny 8–9 bit tokens into wide microinstructions on an FPGA, letting you pack rich behavior into compact code. The post explains visibility ranges, instruction-data representation, and a low-cost way to add a Red-program counter so runs of microcode execute efficiently with minimal hardware overhead.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
The Spartans
Christopher Felton walks through the Spartan6 FPGA basics, explaining CLBs, slices, and the new 6-input LUTs while comparing them to Spartan3. He ran timing-driven mappings of real gateware to show practical LUT utilization differences. The post gives a pragmatic estimate of expected LUT savings and points out where mapping results can vary depending on the design.
How to start in FPGA development? - Simulation software tools
Nuria Orduna lays out a pragmatic approach to FPGA simulation, comparing Xilinx ISE with integrated ModelSim against a three-tool flow with ModelSim and Precision. She explains why independent ModelSim runs and using notepad++ for VHDL can speed debugging, and why Precision and CoreGen conversions can be painful. Read for a compact, practiced workflow to simplify simulation, synthesis, and project organization.
FPGA or DSP Processor - Parameters to Make the Right Choice
Muhammad Yasir breaks down the practical tradeoffs between FPGAs and DSP processors for real-world signal-processing systems. He offers concrete rules of thumb on sampling-rate and data-rate limits, MMAC performance bands, and when conditional logic or floating-point favors a DSP. The post also covers power, form factor, maintainability, and development-time tradeoffs to help architects pick the right platform.
Why I would choose an FPGA development board?
FPGA boards are the smarter choice for hands-on learning and flexible hardware design. Compared with microcontroller dev boards, they let you run many hardware tasks in parallel, reuse the same HDL across different vendors, and even host soft-core microcontrollers inside the fabric. This post walks through those practical advantages and points out modern low-cost boards that make FPGAs accessible for students and engineers.
Feedback Controllers - Making Hardware with Firmware. Part I. Introduction
This first post kicks off a series on using DSP and feedback control with mixed-signal electronics and FPGAs to emulate two-terminal circuits and create low latency controllers. It frames circuit emulation as a feedback problem, highlights latency as the key practical constraint, and outlines the planned evaluation hardware, target devices, and software tools that will be used in later MATLAB/Simulink and FPGA work.
