Use Microprogramming to Save Resources and Increase Functionality
Introduction
Microprogramming is a design approach that every FPGA designer should have in their bag of tricks. I subscribe to the concept that microprogramming is a structured approach to the design of state machines. This is essentially the view of Maurice Wilkes when he first proposed microprogramming in 1951 as an alternative method for the implementation of the control section of a computer. Wilkes was interested in improving the reliability and reducing time needed to implement...
I don’t often convert VHDL to Verilog but when I do ...
VHDL to Verilog
I don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement). For the most part I am HDL agnostic. Well that is not true, I have a strong preference for MyHDL, and an insubstantial preference for VHDL over Verilog. The choice of HDL for a project is often complicated, irrational, sometimes rational, but most often random. It is often not a choice of the developer - for...
Point of View
I was caught of guard when someone commented:
"when a FIR filter is full of multiple loops and complex code, something is wrong"The comment was made during an informal discussion on alternative hardware description languages (HDL) and was targeted to the straightforward FIR filter implemented in MyHDL:
(different FIR description simulation results)
Personally, (and...
MyHDL Presentation Examples
The last two years I presented at EELive. The first year as an overview of MyHDL and a strong case why you should be using MyHDL as your hardware description language (HDL) [paper]. The second year was an introduction to three alternative HDLs (alt.hdl), including MyHDL. I also presented at a regional Python conferene: pyohio. At the Python conference I presented...
Spline interpolation
A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog
IntroductionSplines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...
[Comments] C HLS Benefits
Earlier this week I posted a small write-up comparing a hardware median calculation implemented in a C-to gates "HLS" (Vivado C HLS) and a version in MyHDL. For a long time I have had the belief that C-to-gate technologies are of little to no benefit - based on the simple premise that "C" is not that high-level of a language (I actually consider it lower than Verilog and VHDL ... but that is a conversation for another time).
Language comparisons...
Little to no benefit from C based HLS
Last updated 07-Nov-2015
As I write this I am on a plane and my destination is EELive 2014 where I am going to give a talk hardware design: the grunge era. It is a shotgun introduction to three alternative hardware description languages (alt.hdl). The three languages briefly introduced in the talk are: bsv, chisel, and myhdl. The goal of the talk is simply to raise awareness of the three...
Signed serial-/parallel multiplication
Keywords: Binary signed multiplication implementation, RTL, Verilog, algorithm
Summary- A detailed discussion of bit-level trickstery in signed-signed multiplication
- Algorithm based on Wikipedia example
- Includes a Verilog implementation with parametrized bit width
A straightforward method to multiply two binary numbers is to repeatedly shift the first argument a, and add to a register if the corresponding bit in the other argument b is set. The...
MyHDL Interface Example
MyHDL Interfaces ExampleWith the next release of MyHDL, version 0.9, conversion of interfaces will be supported. In this context an interface is any object with a Signal attribute. This can be used to simplify connection between modules and port definitions. For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:
class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...MyHDL @EDAPlayground
Trying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL.
The @EDAPlayground has two main panels. On the left is the testbench and the right the HDL description to be tested.
There are a couple examples...
PicoBlaze - Program RAM Access for an Interactive Monitor
I have a confession to make: I love PicoBlaze! There are many reasons to love it. It is a tiny CPU (96 Spartan3 slices or 26 Spartan6 slices plus a BRAM). It is simple. It is bug-free. It's pretty fast. It can reduce the size and the complexity of your design - instead of debugging a big state machine, just throw one (or more) of these in. Add a serial output and you can debug your fpga from inside out!However, there are a few problems. The...
StrangeCPU #2. Sliding Window Token Machines
Summary:An in-depth exploration of Sliding Window Token Machines; ARM notes.
Table of Contents:- Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes.
- Part 2: Sliding-Window Token Machines, an in-depth exploration of this curious technology; ARM notes.
- Part 3. Instruction Slides - The Strangest CPU Yet! Decoding instructions with a Sliding Window...
Verilog vs VHDL
Introduction
Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...
Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed
This part in the series will consider the signals, measurements, analyses and configurations for testing high-speed low-latency feedback loops and their controllers. Along with basic test signals, a versatile IFFT signal generation scheme will be discussed and implemented. A simple controller under test will be constructed to demonstrate the analysis principles in preparation for the design and evaluation of specific controllers and closed-loop applications.
Additional design...Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with application examples will be maintained on the project website here.- Part 5: Some FPGA Aspects (this part)
- Part 4: Engineering of...
Launch of Youtube Channel: My First Videos - Embedded World 2017
I went to Embedded World 2017 in Nuremberg with an ambitious plan; I would make video highlights of several exhibits (booths) to be presented to the *Related sites audience. I would try to make the vendors focus their pitch on the essential in order to produce a one to three minutes video per booth.
So far my experience with making videos was limited to family videos, so I knew I had lots of reading to do and lots of Youtube videos and tutorials to watch. Trade shows are...
Ancient History
The other day I was downloading an IDE for a new (to me) OS. When I went to compile some sample code, it failed. I went onto a forum, where I was told "if you read the release notes you'd know that the peripheral libraries are in a legacy download". Well damn! Looking back at my previous versions I realized I must have done that and forgotten about it. Everything changes, and keeping up with it takes time and effort.
When I first started with microprocessors we...
Polynomial Math
Elliptic Curve Cryptography is used as a public key infrastructure to secure credit cards, phones and communications links. All these devices use either FPGA's or embedded microprocessors to compute the algorithms that make the mathematics work. While the math is not hard, it can be confusing the first time you see it. This blog is an introduction to the operations of squaring and computing an inverse over a finite field which are used in computing Elliptic Curve arithmetic. ...
Recruiting New Bloggers!
Previous calls for bloggers have been very successful in recruiting some great communicators - Rick Lyons, Jason Sachs, Victor Yurkovsky, Mike Silva, Markus Nentwig, Gene Breniman, Stephen Friederichs,
3 Good News
Good News #1Last week, I announced a new and ambitious reward program that will be funded by the new Vendors Directory.
This week, I am happy to announce that we have our firsts two sponsors! Quantum Leaps & Abelon Systems have agreed to pay the sponsorship fee to be listed in the new Vendors Directory. Because of their support, there is now some money in the reward pool ($1,000) and enough to pay for the firsts 500 'beers' awarded. Please...
Introducing the VPCIe framework
Introduction
My daily work involves platforms featuring an embedded CPU communcating with a FPGA device over a PCI Express link (PCIe for short). The main purpose of this link is for the CPU to convey configuration, control, and status commands to hardware slaves implemented in the FPGA. For data intensive applications (2D XRay detector readout backend), this link can also be used as a DMA channel to transfer data from the FPGA to the CPU memory. Finally, a slave can interrupt the CPU using...
Windows XP and Win32 - the Platform of the Future!
Over the past decade I often wondered why anyone uses Windows. It's just so... proprietary. And pedestrian. As I grew up my OS of choice went nothing to CPM to DOS (on Apple ][), GEM on Atari ST, MS-DOS, DOS extenders, Mac OS, Windows NT, Windows XP, Linux... Now, I again find myself a fan of Windows XP, the platform of the future. (I am still a fan of bare metal, of course).Maybe I am not totally serious, but I, a self-proclaimed freedom lover and...
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.
Fig 1. The evaluation platform
Additional design...
Live Streaming from Embedded World!
For those of you who won't be attending Embedded World this year, I will try to be your eyes and ears by video streaming live from the show floor.
I am not talking improvised streaming from a phone, but real, high quality HD streaming with a high-end camera and a device that will bond three internet connections (one wifi and two cellular) to ensure a steady, and hopefully reliable, stream. All this to hopefully give those of you who cannot be there in person a virtual...
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator
ESC Boston's Videos are Now Up
In my last blog, I told you about my experience at ESC Boston and the few videos that I was planning to produce and publish. Here they are, please have a look and any feedback (positive or negative) is appreciated.
Short HighlightThis is a very short (one minute) montage of some of the footage that I shot at the show & conference. In future shows, I absolutely need to insert clips here and there of engineers saying a few words about the conference (why they...
Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA
Hi everyone! After a lot of hesitation and several failed attempts, I have finally entered the world of blogging. A little about myself : My name is Sriyash Caculo and I’m a third year undergrad student at BITS Pilani K.K. Birla Goa Campus pursuing a major in Electronics and Instrumentation engineering. Being an electronics engineer, I developed an interest in Digital Signal Processing and its implementation on hardware.
This blog-post is the first of many to come for the...
Launch of EmbeddedRelated.tv
With the upcoming Embedded Word just around the corner, I am very excited to launch the EmbeddedRelated.tv platform.
This is where you will find the schedule for all the live broadcasts that I will be doing from Embedded World next week. Please note that the schedule will be evolving constantly, even during the show, so I suggest your refresh the page often. For instance, I am still unsure if I will be able to do the 'opening of the doors' broadcast as...
Tools of the Trade: reading PDFs (and keeping bookmarks)
In this article I will take a look at the wonderful MuPDF viewer and present a small modification that saves bookmarks alongside the pdf files, making it infinitely more useful.
Some days I sit down to work and wonder how anything ever gets done. A simple example. When I work on an FPGA design, I wind up with 3 or 4 screens full of documentation, generally in PDF format. There are the Xilinx manuals, the various tool manuals, language reference manuals, you name it. While...
