VHDL Coding Styles and Methodologies
VHDL Coding Styles and Methodologies, Edition is a follow up book to the first edition of same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy to read book that gave in depth coverage of both, the language and coding methodologies. This edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD. The CD also includes the GNU toolsuite with EMACS language sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology graciously included a timed evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity included a timed version of Synplify, a very efficient, user friendly and easy to use FPGA synthesis tool. Synplify provides a user both the RTL and gate level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool.
Why Read This Book
You will learn disciplined, reusable VHDL coding patterns that make designs more maintainable, synthesizable, and portable across FPGA toolchains. The book also teaches how to write effective testbenches and bus functional models so your verification flows are robust and reusable.
Who Will Benefit
Hardware designers and verification engineers who already know basic digital logic and want practical guidance on writing synthesis-friendly, maintainable VHDL and testbenches for FPGA projects.
Level: Intermediate — Prerequisites: Basic digital logic and a working familiarity with VHDL syntax and simulation (entity/architecture, signals, processes).
Key Takeaways
- Apply disciplined VHDL coding styles that improve readability, reuse, and maintenance
- Design synthesizable VHDL modules and recognize/avoid non-synthesizable constructs
- Develop structured testbenches and bus functional models (BFMs) for repeatable verification
- Implement robust state machines and parameterized components using VHDL idioms
- Integrate VHDL code with synthesis and simulation tool constraints for FPGA flows
- Employ simulation and debugging techniques to validate and isolate design issues
Topics Covered
- Introduction and objectives: why coding style matters
- VHDL language overview and practical use
- Data types, packages, and designing for reuse
- Processes, concurrency, and clocking styles
- State machine design patterns and best practices
- Coding for synthesis: do's and don'ts
- Hierarchical design, generics, and componentization
- Testbench architecture and bus functional models (BFMs)
- Simulation strategies and debugging techniques
- Integrating with synthesis tools and FPGA considerations
- Examples, case studies, and ready-to-use code
- Appendices: style checklist, coding templates, CD/tool contents
Languages, Platforms & Tools
How It Compares
More hands-on and style-focused than Ashenden's The VHDL® Cookbook/Designer’s Guide to VHDL (which is deeper on language semantics); more practical and methodology-oriented than introductory texts like Perry's VHDL books.
