Field-Programmable Gate Arrays (The Springer International Series in Engineering and Computer Science, 180)
Field-Programmable Gate Arrays (FPGAs) have emerged as an attractive means of implementing logic circuits, providing instant manufacturing turnaround and negligible prototype costs. They hold the promise of replacing much of the VLSI market now held by mask-programmed gate arrays. FPGAs offer an affordable solution for customized VLSI, over a wide variety of applications, and have also opened up new possibilities in designing reconfigurable digital systems.
Field-Programmable Gate Arrays discusses the most important aspects of FPGAs in a textbook manner. It provides the reader with a focused view of the key issues, using a consistent notation and style of presentation. It provides detailed descriptions of commercially available FPGAs and an in-depth treatment of the FPGA architecture and CAD issues that are the subjects of current research.
The material presented is of interest to a variety of readers, including those who are not familiar with FPGA technology, but wish to be introduced to it, as well as those who already have an understanding of FPGAs, but who are interested in learning about the research directions that are of current interest.
Why Read This Book
You should read this book to gain a rigorous, architecture-first understanding of how FPGAs work and why CAD algorithms (mapping, placement, routing) are designed the way they are. It gives you the principled background that helps interpret vendor tools and make defensible design/architecture trade-offs rather than just following recipes.
Who Will Benefit
Engineers and graduate students who design or architect FPGA-based systems and want a solid theoretical and practical grounding in FPGA fabrics and CAD flows.
Level: Intermediate — Prerequisites: Basic digital logic and digital design (combinational/sequential logic), familiarity with boolean algebra and finite-state machines; some comfort with algorithms and complexity will help.
Key Takeaways
- Explain the internal architecture of common FPGA fabrics (LUTs, CLBs, routing, I/O) and the trade-offs involved.
- Analyze the impact of LUT size, interconnect topology, and routing resources on area, speed, and routability.
- Apply and evaluate mapping, placement, and routing algorithms used in FPGA CAD flows.
- Design and reason about memory blocks, I/O structures, and specialized hard blocks in FPGA architectures.
- Assess performance and timing trade-offs and perform basic timing analysis for FPGA implementations.
- Compare commercial FPGA families of the era to understand how architectural choices affect tool flows and designs.
Topics Covered
- Introduction and history of field-programmable devices
- Basic FPGA building blocks: LUTs, PLAs, PLDs
- Configurable logic block architectures and variants
- Interconnect structures and routing channels
- I/O blocks, on-chip RAMs, and dedicated hard macros
- Device-level performance, area, and power trade-offs
- Logic synthesis and technology mapping to FPGA primitives
- Placement strategies and algorithms
- Routing algorithms and timing-driven routing
- Timing analysis, clocking, and performance optimization
- Testing, programming, and reconfiguration issues
- Survey of contemporary commercial FPGAs (historical examples) and case studies
- Future directions and research challenges (as of early 1990s)
Languages, Platforms & Tools
How It Compares
More architectural and CAD-focused than hands-on guides like Pong P. Chu's FPGA prototyping books and more theoretical than practitioner-oriented titles such as Clive Maxfield's Design Warrior's Guide to FPGAs.
