Verilog HDL Synthesis, A Practical Primer
With this book, you can:
- Start writing synthesizable Verilog models quickly.
- See what constructs are supported for synthesis and how these map to hardware so that you can get the desired logic.
- Learn techniques to help avoid having functional mismatches.
- Immediately start using many of the models for commonly used hardware elements described for your own use or modify these for your own application.
Why Read This Book
You should read this book if you need a focused, hands-on guide to writing Verilog that actually synthesizes to the hardware you expect. Bhasker teaches practical coding styles, synthesis-supported constructs, and common pitfalls so you can move from behavioral code to hardware-mapped RTL with confidence.
Who Will Benefit
Practicing FPGA/ASIC designers, hardware engineers, and students who want a practical, synthesis-oriented guide to writing robust Verilog RTL.
Level: Intermediate — Prerequisites: Basic digital logic (combinational/sequential circuits) and familiarity with Verilog syntax and simulation; RTL design concepts are helpful.
Key Takeaways
- Write synthesizable Verilog RTL that maps predictably to gates, registers, and memories
- Recognize which Verilog constructs synthesize and which lead to functional mismatches or tool-dependent behavior
- Design and code FSMs and datapaths in styles that yield good synthesis results
- Infer memories and arithmetic blocks correctly and use vendor primitives when necessary
- Apply synthesis-driven coding techniques to improve area, timing, and tool portability
- Use synthesis directives and constraints effectively to guide tool mapping
Topics Covered
- Introduction: Synthesis vs. Simulation and Coding Discipline
- Verilog Constructs Supported for Synthesis
- Combinational Modeling and Common Pitfalls
- Sequential Logic and Finite State Machines
- Datapath Design: Arithmetic, Shifters, and Multipliers
- Memory Inference: RAMs, ROMs, and FIFOs
- Clocking, Reset Strategies, and Timing Considerations
- Coding Styles for Area and Timing Optimization
- Synthesis Directives, Attributes and Tool Interaction
- Testbench, Verification Notes and Mixed Simulation/Synthesis Issues
- Practical Examples and Common Design Patterns
- Appendices: Synthesis Checklists and Construct Reference
Languages, Platforms & Tools
How It Compares
More synthesis-focused than Samir Palnitkar's Verilog HDL (which is a broader language tutorial); less board-centered and more synthesis-centric than Pong P. Chu's FPGA prototyping books.
