Clocks & Timing

The clock is the heartbeat of every synchronous circuit. On each rising edge, flip-flops all across the FPGA capture new data simultaneously, a beautifully coordinated dance of billions of transistors. But there is a catch: if the data arrives too late, or changes too soon, the flip-flop cannot tell whether it should store a 0 or a 1. The result? Unpredictable, unreliable behavior that can bring an entire design to its knees. Understanding timing is how you prevent that.

Setup & Hold Time Explorer

Drag the yellow data edge left and right to see when timing violations occur. The flip-flop must see stable data before the clock edge (setup time) and after it (hold time):

Understanding Setup and Hold Time

Every flip-flop has two critical timing requirements:

Setup time (t_su) is the minimum time that data must be stable before the rising clock edge. Think of it as the flip-flop needing a moment to “read” the input. If the data is still changing when the clock edge arrives, the flip-flop may capture the old value, the new value, or (worst of all) something in between.

Hold time (t_h) is the minimum time that data must remain stable after the clock edge. Even though the clock edge has already arrived, the internal transistors need the input to hold still for a brief window while they lock the value in.

When either requirement is violated, the flip-flop enters a state called metastability. Its output voltage lands in the forbidden zone between a clean 0 and a clean 1. The output may oscillate, drift slowly to one value, or settle unpredictably. Downstream logic that depends on this output can misinterpret the result, causing cascading errors through your design.

Clock Domain Crossings

Metastability is rare within a single clock domain because FPGA tools ensure all paths meet timing. The real danger appears at clock domain crossings, when a signal generated by one clock is sampled by a different clock. Since the two clocks have no fixed phase relationship, the receiving flip-flop can sample the signal at any moment, including right in the setup/hold window.

The standard defense is a synchronizer: two flip-flops in series on the receiving clock. The first flip-flop may go metastable, but it has a full clock cycle to settle before the second flip-flop samples it. This dramatically reduces (though never fully eliminates) the probability of metastable values propagating into your logic. For multi-bit signals, use gray-coded FIFOs or handshaking protocols instead.

Why This Matters

Timing closure, ensuring every signal path in your design meets setup and hold requirements, is the #1 challenge in real FPGA designs. When your synthesis tool reports a “timing failure,” it means at least one data path is too slow (setup violation) or has a hold problem. Until you fix it, the design may work intermittently or fail under certain conditions. Every professional FPGA engineer spends significant time reading timing reports and optimizing critical paths.