HDL Concepts
Describing hardware with code
When you write software, every line is an instruction that a processor executes one at a time. Hardware Description Languages flip that idea on its head. In HDL, every line describes a piece of physical circuitry: wires, gates, and registers that all exist and operate at the same time. HDL looks like code, but it does not run. It builds. Each statement you write creates real hardware inside the FPGA.
Code-to-Hardware Mapper
Step through simplified HDL-like pseudocode and watch the corresponding circuit build on the right. Each line of code creates a hardware element.
What Is HDL?
HDL stands for Hardware Description Language. The two main HDLs are Verilog and VHDL. Both serve the same purpose: they let you describe a digital circuit in a text file, which tools then translate into actual hardware on an FPGA.
The most important difference from software: concurrency. In a C program, lines execute one after another. In HDL, every assignment and every block describes hardware that exists in parallel. An AND gate and a flip-flop defined on adjacent lines do not take turns. They both operate continuously and simultaneously.
Signals and Wires
In HDL, a signal (VHDL) or wire (Verilog) represents a physical connection, a copper trace on the chip. Assigning a value to a wire does not store it; it establishes a continuous electrical connection. Change the input, and the output changes immediately, just like flipping a light switch.
Continuous Assignment
Statements like assign out = a & b; in Verilog create combinational logic. The output continuously reflects the inputs with no memory or clock involved. These synthesize into gates and wires.
Processes and Always Blocks
Verilog's always @(posedge clk) and VHDL's process(clk) describe sequential logic, circuits that capture values on a clock edge and hold them. These synthesize into flip-flops and registers. The always @(*) form describes combinational behavior, logic that re-evaluates whenever any input changes.
Combinational vs Sequential
This is the central distinction in FPGA design. Combinational circuits are pure logic: outputs depend only on current inputs. Sequential circuits have memory: outputs depend on inputs and the current state, updated on clock edges. Nearly every real design uses both, and HDL gives you clear syntax to specify which you mean.
assign makes wires and gates; an always @(posedge clk) makes flip-flops.
Why This Matters
HDL is the language of FPGA design. Whether you choose Verilog, VHDL, or SystemVerilog, the core concepts are the same: you are describing circuits, not algorithms. Wires carry signals continuously. Always blocks create flip-flops. Everything runs in parallel.
Understanding these concepts, before worrying about syntax, is what separates engineers who write correct hardware from those who write "software in Verilog" and wonder why it does not synthesize. The visualization above captures the essence: one line of HDL, one piece of hardware. That mental model will guide every design you write.
Frequently Asked Questions
What is HDL?
HDL (Hardware Description Language) is a programming language used to describe digital circuits. The two main HDLs are Verilog and VHDL. Unlike software languages that describe sequential steps, HDLs describe parallel hardware: wires, gates, registers, and their connections. The code is not executed; it is synthesized into actual circuit structures that run on an FPGA.
Should I learn Verilog or VHDL?
Both are widely used and equally capable. Verilog has C-like syntax and is dominant in the US and Asia. VHDL has Ada-like syntax and is popular in Europe and defense/aerospace. For beginners, Verilog is often considered easier to start with due to its simpler syntax. SystemVerilog (an extension of Verilog) is increasingly the industry standard, adding modern features for both design and verification.
What is an always block in Verilog?
An always block in Verilog describes behavior that happens repeatedly. "always @(posedge clk)" creates sequential logic: it describes what happens on each rising clock edge, and synthesizes into flip-flops. "always @(*)" creates combinational logic: it re-evaluates whenever any input changes, and synthesizes into gates and wires. Understanding when to use each type is fundamental to writing correct HDL.
Quick Check
Test your understanding of the key concepts from this lesson.
