An FPGA (Field-Programmable Gate Array) is an integrated circuit containing a large array of configurable logic blocks (CLBs), programmable interconnects, and embedded hard IP (such as block RAM, DSP slices, and PLLs) that can be wired together after manufacture to implement a very wide range of digital logic, subject to the device's available LUTs, routing, memory blocks, I/O, and timing resources. Unlike a microcontroller or microprocessor, an FPGA has no fixed instruction stream; its behavior is defined primarily by a configuration bitstream, typically loaded at power-up from flash or another non-volatile source, though external clocks, I/O configuration, resets, and in some devices hard processor content also play a role.
In practice
FPGAs are described using a hardware description language (HDL) -- most commonly VHDL or Verilog, or a higher-level synthesis flow such as Chisel or HLS (High-Level Synthesis). The HDL is synthesized into a netlist, then placed and routed by vendor toolchains (Xilinx/AMD Vivado, Intel/Altera Quartus, Lattice Radiant/Diamond) to produce the bitstream that configures the device. Unlike software compilation, the output is a physical mapping of logic onto silicon resources, and timing closure -- ensuring all paths meet setup and hold requirements -- is a central concern.
In embedded systems, FPGAs appear in roles where a fixed-function MCU or DSP is insufficient: custom high-speed interfaces (PCIe, JESD204B, and proprietary protocols implemented over hardened SerDes transceivers), real-time signal processing pipelines (SDR, radar, motor control with sub-microsecond loop times), protocol bridging, and co-processing alongside a hard or soft CPU. Devices such as the Xilinx Zynq-7000 and Zynq UltraScale+ integrate hard ARM Cortex-A cores with FPGA fabric on the same die, blurring the line between SoC and FPGA. Lattice iCE40 and ECP5 parts occupy the low-power, small-footprint end of the spectrum and are popular in open-source toolchain communities.
A critical operational difference from MCUs is that FPGAs are inherently volatile in most families -- SRAM-based configuration is lost at power-down, so an external configuration flash (SPI NOR or dedicated quad-SPI device) is almost always required in a production design. Antifuse FPGAs (e.g., Microsemi/Microchip ProASIC3, IGLOO) are non-volatile, and certain families are qualified for radiation-tolerant applications, which makes them used in aerospace and defense contexts. Configuration time (tens of milliseconds to several seconds depending on bitstream size and interface speed) must be accounted for in system bring-up sequencing.
Common pitfalls include underestimating resource utilization until after place-and-route, timing failures that only surface at temperature or voltage extremes, and incorrect handling of clock domain crossings (CDC) -- metastability from unsynchronized signals between clock domains is a leading source of subtle FPGA bugs. Simulation (behavioral and post-synthesis gate-level) and formal verification are standard mitigation steps. For developers coming from a software or MCU background, the shift to thinking in concurrent, clocked hardware rather than sequential instructions is the largest conceptual hurdle; the blog post "Introduction to FPGA Technology" is a useful starting point.
Learn this in FPGA Fundamentals
Discussed on FPGARelated
Frequently asked
How is an FPGA different from a microcontroller?
A microcontroller contains a fixed CPU whose core execution model is sequential (fetch-decode-execute), even though the surrounding system may include DMA engines, accelerators, or multiple cores. An FPGA implements logic structurally: you define what hardware circuits exist and how they connect. There is no fetch-decode-execute cycle unless you explicitly synthesize a soft-core CPU into the fabric. This means an FPGA can execute many operations in true parallel, but it also means every function must be designed as hardware, not written as software.
What is the difference between an FPGA and an ASIC?
An
ASIC (Application-Specific Integrated Circuit) is a chip with a permanently fixed layout, manufactured for a specific function. An FPGA's logic is configurable and can be reprogrammed. ASICs offer lower unit cost at volume, better performance per watt, and higher logic density, but require costly mask sets (often millions of dollars for advanced nodes) and long lead times. FPGAs are used for prototyping, lower-volume production, and applications requiring field updates.
Can you run software on an FPGA?
Yes, in two ways. First, many mid-range and high-end FPGAs include hard processor cores -- the Xilinx Zynq-7000 has dual Cortex-A9 cores, and Intel Cyclone V SoC parts include Cortex-A9 as well. Second, you can synthesize a soft-core CPU -- such as a RISC-V core,
MicroBlaze (Xilinx), or Nios II (Intel) -- directly into the FPGA fabric and run firmware on it. Soft cores consume fabric resources and run slower than hard cores, but offer flexibility.
What does 'configuring' an FPGA mean in a production system?
Most FPGAs based on SRAM technology (the large majority of commercial parts) lose their configuration when powered off. On power-up, the device reads its
bitstream from an external source -- typically a dedicated
SPI NOR flash or a connected host processor -- and configures its internal SRAM cells. This process typically takes from a few milliseconds (small iCE40 parts) to a few seconds (large UltraScale+ devices). Your board design and power sequencing must account for this configuration latency before the FPGA logic becomes functional.
Is FPGA development suitable for someone with only MCU firmware experience?
It is accessible but requires a genuine mental model shift. MCU firmware is sequential; FPGA design is concurrent and structural. You must think about clock domains, pipeline stages, and timing budgets rather than execution time. Starting with a well-supported development board and a project like a simple UART controller or
SPI peripheral is a practical approach -- the blog post 'Why I would choose an FPGA development board?' discusses considerations for getting started.
Differentiators vs similar concepts
FPGA vs.
CPLD: CPLDs (Complex Programmable Logic Devices -- e.g., Xilinx CoolRunner-II, Lattice ispMACH 4000) are an older, simpler class of programmable logic. CPLDs typically use a sum-of-products (AND-OR) architecture with a small number of macrocells (tens to a few hundred), are non-volatile (configuration stored in on-chip flash or EEPROM), and offer deterministic, near-instantaneous pin-to-pin propagation delay. FPGAs use
LUT-based fabric, scale to millions of equivalent gates, include hard blocks (
block RAM, DSP
slices,
PLLs, high-speed SerDes), and are generally SRAM-based (volatile). CPLDs suit simple glue logic and boot sequencing; FPGAs suit complex digital designs. The boundary has blurred as vendors discontinued many CPLD lines. FPGA vs. ASSP/SoC: An application-specific standard product (ASSP) or SoC implements a fixed function in silicon with no reconfigurability; an FPGA trades density and power efficiency for flexibility and field-reprogrammability.
