A Phase-Locked Loop (PLL) is a feedback control circuit that locks the phase (and therefore frequency) of an output signal to a reference signal, typically used to multiply, divide, or clean up clock frequencies. PLLs are found in microcontrollers, SoCs, and FPGAs to generate high-frequency system clocks from a lower-frequency crystal reference.
In practice
In most embedded systems, the raw oscillator or crystal frequency (commonly 8 MHz, 12 MHz, or 16 MHz on MCU boards) is not the target system clock frequency. The PLL takes that reference, multiplies it by a configurable factor (integer-only on many MCU PLLs, fractional on others), and produces a stable, higher-frequency output. On an STM32F4, for example, a 16 MHz HSI or external crystal can be routed through the PLL with VCO multiplier and divider registers to produce a 168 MHz CPU clock on supported variants. Similar schemes exist on NXP i.MX RT, Microchip SAM, and Nordic nRF53 devices.
Configuration typically involves setting at minimum an input divider (M), a VCO multiplier (N), and one or more output dividers (P, Q, R on STM32 parts), and then waiting for a lock-detected flag before switching the system clock source. Failing to wait for lock, or feeding out-of-spec frequencies into the VCO, produces an unstable or absent clock with no exception or error -- the CPU just runs incorrectly or halts.
PLLs also appear in FPGAs, where dedicated PLL or MMCM (Mixed-Mode Clock Manager) primitives on devices such as Xilinx Spartan-6/7, Intel Cyclone, and Lattice ECP5 families generate phase-shifted or frequency-divided clocks for use across clock domains (though proper synchronizers or FIFOs are still required to safely cross between those domains). Because PLL output jitter and phase noise are measurable quantities, high-speed peripherals (USB, Ethernet, SD/SDIO) often require the clock to be sourced from a dedicated PLL output rather than a divided general-purpose clock.
A common pitfall in low-power designs is that most PLLs consume continuous current (often 1--10 mA), have a non-negligible lock time on wake from sleep (typically tens to hundreds of microseconds), and cannot operate below a minimum VCO frequency. Systems that need fast wake times or must minimize active current sometimes run directly from a divided crystal oscillator during short active windows, bypassing the PLL entirely.
Frequently asked
Why does my MCU fail to boot or run erratically after I changed the PLL settings?
The most common causes are: not waiting for the PLL lock flag before switching the system clock source, configuring the VCO outside its allowed input or output frequency range, or setting flash wait states too low for the new clock frequency. On STM32 devices, for example, the reference manual specifies minimum flash latency per voltage/frequency operating point -- skipping this step causes random instruction fetch failures even though the PLL locks correctly.
What is the difference between a PLL and an FLL (Frequency-Locked Loop)?
A PLL controls the phase of the output, which implies frequency lock as a consequence. An FLL controls frequency more directly and does not correct sub-cycle phase error. In practice the distinction is not always absolute, as some implementations are hybrids, but as a useful approximation: FLLs are simpler, consume less power, and are common on MSP430 devices (via the DCO and FLL+ modules), while PLLs typically produce lower
jitter because they do correct phase error within each cycle.
Can I use the PLL output directly for USB or other protocol-specific peripherals?
Usually yes, but the PLL must be configured to produce the exact required frequency. USB full-speed requires a 48 MHz clock with tight accuracy (within approximately 0.25% for crystal-derived sources, though the exact tolerance depends on the device and whether clock recovery is involved). STM32, SAM, and similar parts expose a dedicated PLL output divider (often called PLLQ or PLL48CLK) for exactly this purpose. Getting the wrong frequency silently causes USB enumeration failures.
How do PLLs work in FPGAs compared to MCUs?
FPGA PLLs (called
MMCM, CMT, or just PLL depending on vendor and family) are instantiated as hard primitives inside the device and configured through the
synthesis tool rather than runtime registers. They offer multiple independent phase-shifted output clocks, fine phase adjustment, and dynamic
reconfiguration on higher-end families. The blog post 'Designing a FPGA Micro Pt2 - Clock and Counter build and test.' touches on building clocking infrastructure around these primitives.
What is a DPLL and how does it differ from an analog PLL?
A Digital PLL (DPLL) implements the loop filter and phase comparison in the digital domain, often using a numerically controlled
oscillator (NCO) instead of a voltage-controlled oscillator. This makes it easier to implement in software or logic and avoids analog component variation, at the cost of quantization noise and discrete phase steps. The blog post 'Use DPLL to Lock Digital Oscillator to 1PPS Signal' demonstrates locking a software oscillator to a GPS 1PPS reference using this approach.
Differentiators vs similar concepts
A PLL is often confused with an FLL (Frequency-Locked Loop) and with a simple clock divider/
multiplier. A clock divider produces only integer sub-multiples of the input and has no feedback loop. An FLL (used on MSP430 DCO, for example) locks frequency but not phase, resulting in higher
jitter. A PLL locks phase, which guarantees frequency lock and typically produces lower jitter than an FLL. The term DPLL (Digital PLL) refers to a PLL whose loop filter and comparator are implemented digitally, not to a different fundamental function.
