HDL synthesis is the process by which a hardware description language (HDL) source file -- written in VHDL, Verilog, or SystemVerilog -- is automatically translated by a synthesis tool into a gate-level netlist targeting a specific technology library (standard cells for ASICs or lookup tables and hard blocks for FPGAs). The resulting netlist is a logical representation of the design that can be placed, routed, and ultimately implemented in silicon or programmable fabric through subsequent implementation steps.
In practice
In a typical FPGA design flow, synthesis is the first major compilation step. FPGA tools such as Xilinx Vivado, Intel Quartus Prime, and Lattice Radiant read the HDL source and produce a technology-mapped netlist; dedicated ASIC synthesis tools such as Synopsys Design Compiler serve a similar role but target foundry standard-cell libraries and may expose synthesis and technology mapping as more distinct phases. The synthesis tool applies logic optimization passes -- Boolean minimization, resource sharing, retiming -- before mapping logic to the target device's primitives (LUTs, DSP blocks, block RAM, etc.). The quality of results (QoR) in terms of timing, area, and power is heavily influenced by both how the HDL is written and the constraints provided to the tool.
Not all valid HDL is synthesizable. Constructs that are fine for simulation -- such as delays specified with `#` in Verilog, certain file I/O calls, or dynamic memory allocation -- are typically ignored or rejected by synthesis tools, though some vendors may handle limited subsets of such constructs in tool-specific ways. Developers must write RTL (Register Transfer Level) code that describes behavior in terms of clocked registers and combinational logic. Common pitfalls include unintended latches generated from incomplete `if/else` or `case` statements, and clock-domain crossings that simulate correctly but fail in hardware.
Synthesis tools consume timing constraint files (XDC for Xilinx, SDC for most others) to guide optimization. These constraints specify target clock frequencies, input/output timing budgets, and path exceptions, though path exceptions and detailed timing intent are consumed across synthesis, optimization, and place-and-route rather than by synthesis alone. Without accurate constraints, the tool may produce a netlist that meets no meaningful timing target. Post-synthesis timing analysis gives a first estimate of timing closure, though the final sign-off typically comes after place-and-route when actual routing delays are known.
Alternative HDL flows are also synthesizable on modern tools. Python-based hardware description languages such as MyHDL can generate VHDL or Verilog that is then handed off to a conventional synthesis tool. High-Level Synthesis (HLS) tools such as Vitis HLS or Catapult take C/C++ or SystemC as input and produce RTL, adding another layer before conventional synthesis. The tradeoffs of that approach are discussed in "[Comments] C HLS Benefits."
Discussed on FPGARelated
Frequently asked
What is the difference between synthesis and simulation?
Simulation executes
HDL behaviorally to verify functional correctness; it has no knowledge of the target device and supports the full HDL language. Synthesis translates a synthesizable subset of HDL into a gate-level
netlist for a specific technology. A design can simulate correctly and still fail synthesis if it uses non-synthesizable constructs, or fail in hardware if simulation did not account for real timing.
Why does synthesis sometimes infer a latch when I didn't intend one?
In
combinational logic blocks, if a signal is not assigned under every possible condition -- for example, an `if` without a matching `else`, or a `case` that doesn't cover all values and lacks a `default` -- most synthesis tools infer a
latch to hold the previous value. Latches are often undesirable in synchronous designs because they complicate timing analysis. The fix is to ensure complete assignment coverage or to add a `default` clause.
What are timing constraints and why are they required?
Timing constraints, typically written in SDC (Synopsys Design Constraints) format or the Xilinx XDC variant, tell the synthesis tool the target clock frequencies, input/output timing budgets, and any paths to be treated as exceptions. Without them, the tool has no optimization target and may produce a
netlist with no guarantee of meeting any specific speed. Accurate constraints are essential for meaningful timing-driven optimization and for catching setup/hold violations early.
Can I synthesize HDL generated by a higher-level tool like MyHDL or an HLS tool?
Yes. Tools like MyHDL generate standard
VHDL or
Verilog that is then passed to a conventional synthesis tool unchanged -- the synthesis tool has no awareness of the upstream generator.
HLS tools such as Xilinx Vitis HLS similarly emit
RTL that feeds into the normal synthesis flow. The quality of the resulting
netlist depends on how well the generated RTL maps to the target technology, which varies by tool and coding style.
What is the difference between RTL synthesis and technology mapping?
These are two phases within the overall synthesis process.
RTL synthesis converts the
HDL description into a technology-independent
netlist of generic logic operations (AND, OR,
flip-flops, multiplexers). Technology mapping then replaces those generic elements with the actual primitives available in the target library --
LUTs and flip-flops on an
FPGA, or standard cells from a foundry library for an
ASIC. Some tools expose these as separate steps; others combine them into a single pass.
Differentiators vs similar concepts
Synthesis is often conflated with the broader "compilation" flow in
FPGA tools, which also includes place-and-route (P&R) and
bitstream generation. Synthesis alone produces a
netlist; it does not assign logic to physical locations or route interconnect -- that is the job of the place-and-route stage. Timing results from synthesis are estimates based on wire-load models or ideal routing; final timing sign-off requires post-route analysis with actual interconnect delays. Synthesis is also distinct from
simulation: simulation verifies behavior, synthesis produces hardware. Finally, synthesis should not be confused with
High-Level Synthesis (HLS), which compiles algorithmic C/C++ code into
RTL as a precursor to conventional RTL synthesis.
