Verilog is a hardware description language (HDL) used to model, simulate, and synthesize digital logic, from individual gates up to complete system-on-chip designs. It describes hardware behavior and structure concurrently rather than sequentially, reflecting how real digital circuits operate.
In practice
In embedded systems work, Verilog is most commonly used when the target device is an FPGA or CPLD rather than a fixed-function MCU. Designers write synthesizable Verilog to implement custom peripherals, signal processing pipelines, communication interfaces, or entire soft-core processors. Tools from vendors such as Xilinx (Vivado), Intel/Altera (Quartus), and Lattice (Radiant, iCEcube2) accept Verilog as a primary input format and synthesize it to the device's fabric.
Verilog code is organized primarily into modules, which are the basic building blocks of any design. A module declares its ports, then describes internal logic using continuous assignments (`assign`), procedural blocks (`always`, `initial`), and instantiations of other modules. The `always @(posedge clk)` idiom for clocked registers and `always @(*)` for combinational logic are the two patterns that appear in almost every synthesizable design. SystemVerilog, a superset standardized in IEEE 1800, extends Verilog with stronger typing, interfaces, and rich verification constructs, and is now supported by most major synthesis and simulation tools.
A common pitfall for developers new to Verilog is conflating simulation semantics with synthesis semantics. Constructs like delays (`#10`) and certain `always` coding styles are valid in simulation but are either ignored or rejected by synthesis tools. `initial` blocks are generally simulation-only, though some FPGA synthesis flows do support them in limited contexts for initialization; behavior is tool-dependent. Another frequent issue is unintended latch inference: in a combinational `always` block, failing to assign an output under every branch of conditional logic causes a synthesis tool to infer a latch, which is usually not what the designer intended.
For embedded developers crossing over from C or assembly, the hardest conceptual shift is that all `always` blocks and `assign` statements execute concurrently. Reading Verilog as if it were sequential code leads to incorrect mental models and subtle bugs. Simulation with a tool such as Icarus Verilog, Verilator, or the vendor's bundled simulator, combined with waveform inspection, is the standard way to verify behavior before committing to hardware.
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Discussed on FPGARelated
Frequently asked
What is the difference between Verilog and VHDL?
Both are IEEE-standardized HDLs capable of describing the same hardware. Verilog uses a C-like syntax and is generally considered more concise;
VHDL uses a strongly typed Ada-like syntax that catches more errors at compile time. Verilog tends to be more prevalent in North American industry and
ASIC design, while VHDL has historically seen heavier use in European and defense/aerospace contexts, though this varies considerably by company, domain, and region. The blog post 'Verilog vs VHDL' on EmbeddedRelated covers the practical tradeoffs in depth. For new projects, tool support and team familiarity are typically the deciding factors.
What is SystemVerilog, and do I need it?
SystemVerilog (IEEE 1800) is a superset of Verilog (IEEE 1364) that adds features in two areas: design (interfaces, packed structs, enums, always_ff/always_comb/always_
latch keywords) and verification (classes, constrained-random stimulus, functional coverage, assertions). For
RTL design targeting FPGAs, the design-side additions -- especially always_ff and always_comb -- improve
synthesis intent clarity and are worth adopting. The verification features are more relevant to large
ASIC teams. Most modern
FPGA tools accept synthesizable SystemVerilog.
What does 'synthesizable' mean, and why does it matter?
Synthesizable Verilog is the subset of the language that a
synthesis tool can translate into actual gates or
FPGA primitives. Many valid Verilog constructs -- delays, file I/O, `initial` blocks in most contexts -- are meaningful only in
simulation. Writing non-synthesizable constructs in your
RTL will either produce a tool error or be silently ignored, resulting in a mismatch between simulated and real hardware behavior.
How do I simulate Verilog without a vendor tool?
Icarus Verilog (iverilog) is a free, open-source compiler and
simulator that handles most synthesizable Verilog and some
SystemVerilog. GTKWave is commonly paired with it for waveform viewing. Verilator is another open-source option that compiles Verilog to C++ for fast cycle-accurate simulation, though it requires writing a C++
testbench harness. Vendor tools (
Vivado Simulator, ModelSim/Questa, Xcelium) offer fuller language coverage and are typically used for larger or mixed-language projects.
Can Verilog be used to program microcontrollers?
Not directly. Verilog describes hardware structure and behavior; it is synthesized to configure an
FPGA's programmable fabric or to produce a
netlist for an
ASIC. It does not compile to machine code for a fixed-function MCU. However, a soft-core processor (for example, a RISC-V or
MicroBlaze core) can be implemented in Verilog on an FPGA, and that processor then runs conventional embedded firmware.
Differentiators vs similar concepts
Verilog is often compared to
VHDL, the other dominant
HDL. The two languages target identical problem domains and both have IEEE standards; the differences are syntactic style, type system strictness, and ecosystem conventions rather than fundamental capability.
SystemVerilog (IEEE 1800) is a superset of Verilog (IEEE 1364) and not a separate language -- in practice, valid Verilog is valid SystemVerilog in most tools, though versioning differences between the two standards mean they are not unconditionally interchangeable in every tool or context. Verilog should not be confused with
HLS (High-Level
Synthesis) languages like Xilinx Vitis HLS or Intel HLS Compiler, which synthesize C/C++ to
RTL; those tools may generate Verilog as an intermediate output, but the designer writes C, not Verilog.
