Hi , i am new to the memory modules .I want to study about DDR Rams . So please send me the links to study in depth about various rams and...

Hi , i am new to the memory modules .I want to study about DDR Rams . So please send me the links to study in depth about various rams and their controllers, Vits

Looking for information about the old (Zilog) application note "Memory Management and the Z80,000 32-bit Microprocessor" (Zilog document number...

Looking for information about the old (Zilog) application note "Memory Management and the Z80,000 32-bit Microprocessor" (Zilog document number 00-2329-01).

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free...

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free Read DC software yesterday? Thank you. Weng

In a design, I have a number of counters that have an enable that is only active every N periods of the clock signal. With only a clock...

In a design, I have a number of counters that have an enable that is only active every N periods of the clock signal. With only a clock of 200MHz in the timing constraints, the counters are assumed to run at 200MHz and timing fails. As these counters actually run at much lower speed, I know they will work. But how to convince the tools (Lattice iCEcube2) that all is OK? I am trying to add ...

my project designing a vending machine that sells a candy for 40 cent. it accept olny 5 cent(N) and 10 cent (D). and the candy i wrote this code...

my project designing a vending machine that sells a candy for 40 cent. it accept olny 5 cent(N) and 10 cent (D). and the candy i wrote this code for this but i couldn't write a testbench to see waveform Can you help me please library ieee; use ieee.std_logic_1164.all; entity vending_machine is port ( CLK, RESET: in std_logic; N, D: in std_logic; output: out std_logic; ...

I need to generate a programming file for an older XC7300 series chip using an existing Abel and/or PLD file. As far I know, only XactStep 6 and...

I need to generate a programming file for an older XC7300 series chip using an existing Abel and/or PLD file. As far I know, only XactStep 6 and Foundation 1.3 supported those chips as Foundation 1.4 doesn't have options for them any more. I have hardware dongles for the software but no license file so a couple of questions :). 1) Do the hardware dongles still require a LICENSE.DAT file? I kno...

I Need Help To Solve This project Need to write FPGA Source code

I Need Help To Solve This project Need to write FPGA Source code

This is a bit of the chicken and egg thing. If you want a embed the code checksum in a code module to report the checksum, is there a way of...

This is a bit of the chicken and egg thing. If you want a embed the code checksum in a code module to report the checksum, is there a way of doing this? It's a bit like being your own grandfather, I think. I'm not thinking anything too fancy, like a CRC, but rather a simple modulo N addition, maybe N being 2^16. I keep thinking of using a placeholder, but that doesn't seem

Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone know of a mirror or a...

Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone know of a mirror or a way to obtain old versions? You cannot download from the site anymore. Chris

A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my...

A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my customer has said "no" to the 100% Chinese brand... US government customers, ya know! So now I'm looking at a BGA. I don't want to get into fine PCB design rules, so 1.0 mm ball pitch is my preference. The only devices I can find tha