Intel announces new FPGA families

https://fpgaer.tech/?p=561

On Thursday, September 29, 2022 at 12:05:09 PM UTC-4, claudio...@gmail.com wrote:
> https://fpgaer.tech/?p=561

Maybe I'm just old, but it seems to me "new" in the FPGA world is not very inspiring.  I guess I'm really saying I don't know diddly about '“R” transceiver tiles', CXL v2.0, or "hardened time-sensitive network controllers".  

Yup, I'ma gittin' old. 

-- 

Rick C.

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gnuarm.del...@gmail.com <gnuarm.deletethisbit@gmail.com> wrote:
> On Thursday, September 29, 2022 at 12:05:09 PM UTC-4, claudio...@gmail.com wrote:
> > https://fpgaer.tech/?pV1
> 
> Maybe I'm just old, but it seems to me "new" in the FPGA world is not very
> inspiring.  I guess I'm really saying I don't know diddly about '&ldquo;R&rdquo;
> transceiver tiles', CXL v2.0, or "hardened time-sensitive network
> controllers".
> 
> Yup, I'ma gittin' old. 

I think the FPGA market has bifurcated into (at least) two quite distinct
markets:

- the small, low cost, low power segment, where people want a programmable
  chip of the scale of a small CPU like a Z80 or an m68k, maybe in a small
  package like a BGA256.  Quite a lot of crossover with CPLDs.
- the server/etc market where the chips are as complex, expensive and power
  hungry as a modern Xeon

Since being bought by Intel, Altera seemingly have pushed strongly towards
the latter - not terribly surprising given it's Intel.

For the former, I think we increasingly have to look away from Altera and
Xilinx and towards the smaller players like Lattice and Microsemi, and maybe
some of the Chinese firms.

Theo