I have an application using a Lattice UltraPlus FPGA which is mostly working except for some marginal behavior. I'm pretty sure it's due to timing constraint issues (at present I have no timing constraints implemented). I'm new to specifying those and so it's a bit daunting to figure out how to resolve these issues.
a) If anyone can point me to a good resource that shows how to arrive at what constraints are needed in a design that would be great. The syntax and details of implementing the constraints are readily available it's knowing what constraints to specify that's at issue...
b) If anyone has "significant" experience with doing this and wants to make some extra cash looking over my design and helping me work out the constraints to resolve my issues I'd be happy to pay for the help.
c) If anyone has any other ideas that might help, I'm open to them.
The main principle of timing constraints are:
1) tell the tool what is your base clock(s) frequency i.e. those clocks that enter from fpga pins rather than any generated internally which are not recommended except through PLL.
e.g. create_clock -period ....this determines correct constraint for internal paths.
2) tell the tool how the i/o should behave with respect to data transition relative to its clock e.g. set_input_delay....set_output_delay
3) in some cases you may add further info such as multicycle, false paths...
That's a great overview, but I think I'm going to have to find someone with specific knowledge working with this tool and perhaps this part to help me get things setup correctly.
If you know anyone that can help please let me know,
I am afraid I can't help with specific lattice environment. However I believe Lattice follows .sdc (synopsis design constraints) file.
You can try at least define your clock. Normally I will do it like this:
assuming your clock port at top level is named clk1 of period 20 ns then
create_clock -period 20 -name myclk [get_ports clk1]
save that as a file with extension .sdc and add to your project
I'm using the onboard oscillator as my timebase there may well be some slop in the timebase part to part.
Question regarding this: I also dealed with the ULTRAPLUS recently and found it difficult to follow this particular design flow since there seemed to be more than one way and points of the ide where and when to apply constraints. Is there a straight forward design stat to do that?
I found that the tool creates such constraints automatically after having found the clock and offers to apply them. (?)
Also I recognized that the IDE did not get an update after 2020 yet. (More than 2 years now) Is that right?