with reference to the following article,
https://www.dsprelated.com/showthread/comp.dsp/727...
I have understood that decimating doesn't destroy the processing gain achieved in ADC after suitable placing a Digital FIR filter after ADC.
I'm using a FPGA. My ADC is 12bit. In my case, a signal of Bandwidth 25KHz is sampled @60MSPS(due to certain constraints). As, it is difficult to design a filter of BW 25KHz at 60MSPS, I have used a CIC decimator. The 12 bit ADC sampled signal(Sampling rate 60MSPS) is decimated by 60 to get 1MSPS. Now, the decimated 1MSPS signal is passed through a FIR filter(25KHz BW).
As per my understanding,
the processing gain=10log(60MSPS/(2*25KHz))
=30dB
For every 6 dB of SNR one bit is required. So, a total of 5 extra Bits(30dB/6dB) are required.
Q1) Am I right in saying that my output variable(after decimating and FIR filtering) need to be only 12 bits (ADC bits) plus 5bits(from processing gain) i.e 17 bits?
Q2)Now, coming to my doubt in implementation point of view.
12 bit ADC signal(BW =25KHz) sampled @ 60MSPS, is passed through a CIC decimator of decimation value 60. The output of CIC decimator is giving 30 bits(maintaining Full Precision).
Here, do I need to retain entire 30 bits or just the 17 bits(12 ADC bits plus 5 bits from Processing gain). Will I be able to retain the processing gain achieved in both cases?
Q3)Lets assume, all the 30 bits from CIC decimator are retained. Now, the output of CIC is passed through a FIR filter(BW=25KZ). The filter(Xilinx FIR IP core) in-turn gives an output filtered variable of bit width 49. How many bits can I sacrifice at this stage, in order not to loose the processing gain and also not to over design the system?
Thanks.
I will suggest this:
Pass 12 bits data through cic and target 12 bits final output with input/output power unity as a starting point. In the same way treat fir as 12 bits in/out with full internal bit growth and power unity across input/output.
12 bits should get you about 72 dB snr. is that enough. If not get more than 12 bits from cic e.g. 16 bits and maintain 16 bits through. that will get you 16*6 db SNR. From where?
since you are decimating by 60 you have room for about 2^5 to 2^6 to extract from adc rate but no more. so 16 bits will do well. I think that is what is called processing gain or is it?
Hi,
Q1)Pass 12 bits data through cic and target 12 bits final output with
input/output power unity as a starting point. In the same way treat fir
as 12 bits in/out with full internal bit growth and power unity across
input/output.
>I just wanted to know, how the processing gain is realized in terms of bits. The processing gain, will it be within the 12 bits of ADC or do I need to add extra bits(5 bits) equivalent of processing gain(30dB/6dB=5bits).
Let, me clarify my problem once again.
Let N be no:of bits of ADC,
SNR =6.02*N +1.76dB + Processing Gain
processing gain=10log(fs/(2*BW)) ; { fs=60MSPS, BW=25KHz}
=10log(60MSPS/(2*25KHz))
=30dB
For this 30dB, do I need to add only extra 5 bits(30dB/6dB) for my output variable (after CIC and filtering), so that it becomes 12+5=17 bits.
As you mentioned, if unity gain filter's are designed, then output bit width is at 12 bits only, then what is happening to the Processing Gain bits(5 bits)?
Please clarify.
Q2)If not get more than 12 bits from cic e.g. 16 bits and maintain 16 bits through. that will get you 16*6 db SNR. From where?
>I thinks, its answered in the following link.
https://www.dsprelated.com/showthread/comp.dsp/727...
Thanks.
If you want full use of processing gain then do that at CIC stage. In this case you need to get 17 bits out of CIC and maintain that to FIR and after.
To get 17 bits dynamic range out, your CIC power gain must be square(2^5) instead of unity. As such all 17 bits will be occupied by information from CIC internal computations.
Anything more than 17 bits is waste as it becomes just scaling with no information in LSBs.
I still say that if 72dB is enough you can give up on processing gain. just get 12 bits out of CIC based on power gain of 1 instead of square(2^5).
In any case you can model your design in software(matlab/Octave) then see what is happening to dynamic range before going to implementation stage on FPGA. Your main guide for scaling would be input to output power.
