Generating a Block Design in Vivado from existing Verilog & IP files

Started by wlarsen 8 years ago2 replieslatest reply 8 years ago6264 views

I have a #Vivado project that I pieced together from #Verilog and IP files from a Github repository. I believe the project was originally created in ISE as there is no Tcl file to run and regenerate the original block design from. I am looking for a way to generate the block design from the existing Verilog and IP because even though I am able to synthesize the project, run implementation, and generate a bitstream, I am unable to export the bitstream to SDK because without a block design, the .sysdef and .hwdef files are never created so there is no hardware handoff for the SDK. I even tried running the Tcl commands to force Vivado to generate the .sysdef and .hwdef files despite the fact the commands are automatically run after generation of the bitstream and implementation, and I am still unable to export the bitstream to SDK.

I have been through many forums and I'm beginning to think I may be trying to do the impossible here. I was curious if anyone else had found a work-around.

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Reply by oliviertApril 23, 2016


I think you should first package your own Verilog IPs into IPXact and then recreate the block design.

In order to do so you have the User Guide UG1119 and the associated tutorial UG1118.



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Reply by adamt99April 23, 2016


If you have all HDL files in verilog or VHDL you can just write a top level file which performs the instantiation and port mapping (to use VHDL terms) and connects the modules together you do not have to use the Block Diagram editor to create your design. 

It should then synthesise and implement OK - after all the block diagram results in a HDL file being created for implementation anyway.

Hope this helps