Overloading assignment operator '<=' in vhdl

Started by LabPe43 7 years ago1 replylatest reply 7 years ago427 views

I wonder whether I can get any help in overloading the assignment operator '<=' between std_logic_vector and record

record signal <= std logic vector signal


[ - ]
Reply by asserMay 15, 2017

the operator '<=' is overloaded for any type of the signal.

But the left and right sides must be of the equal type or be subtype of this type.

You can assign the components of the record separately, like:

type comp is record (re,im:integer);

signal A: comp;

A.re<= 1000; A.im<=0;