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Timing constraints priority

Started by kaz 7 years ago1 replylatest reply 7 years ago1256 views

Hi All,

I am trying to understand an issue with synopsis timing constraints priority (TimeQuest in fact). 

Suppose I set clock group command to say clk1 is unrelated to any other clock in the system. This will mean that all paths between clk1 and any other clock are false. However there might be other commands across clk1 domain to other clocks such as those in dual clock fifos (set by ip) or any max skew commands (set by user) on such paths, How is the priority decided under such multiple commands on same path. 

I know command priority is given to false path but can this be true with clock group command? I also know the occurrence of a command in file list may overwrite previous command but the overall picture is not clear to me.

Any help appreciated.

Thanks


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Reply by kazNovember 29, 2017

I found some information from "Vivado Design Suite User Guide Using Constraints" 

It says:

****************

"The set_max_delay command can also be used to constrain asynchronous signals that: (1) do not have a clock relationship; but which (2) require maximum delay. For example, timing paths between two asynchronous clock domains can be disabled with the set_clock_groups command (recommended) or the set_false_path command (not recommended). This assumes that you have properly designed the inter-clock domains with, for instance, a double registers synchronizer or a FIFO. However, you must still ensure that the path delay between the two clock domains is not unnecessarily high. If a maximum delay must be specified for some or for all the paths between two clock domains, then you must use the command set_max_delay -datapath_only to constrain those paths. In this case, set_clock_groups cannot be used to define the two clock domains as asynchronous, as it supersedes the set_max_delay constraint in terms of constraint priority. Other cross clock domains paths must then be constrained with a combination of set_false_path or set_max_delay constraints.

"

*****************

However it is not what I as designer wanted to hear?? 

Moreover, how then dual clock fifos seem to work and do not get reported timing failures on the set_max_delay or set_max_skew set by ip itself when I set their clocks as unrelated groups. 

Something is not consistent here across tools may be...


edit:

By the way reading back the first section seems contradicting itself as to the recommended use.