VHDL Matrix Multiplication using UART and BRAM
Started by 8 years ago●2 replies●latest reply 8 years ago●608 viewsA beginner FPGA developer is seeking guidance on implementing matrix multiplication in VHDL on a Basys 3 board using UART for data transfer and BRAM for storage. The discussion focuses on the architectural design, specifically how to coordinate data flow between the serial interface and the processing unit.
Recommendations include using a state machine to manage the UART-to-BRAM data transfer and selecting appropriate BRAM configurations for storing input and output matrices.
- Implement a finite state machine (FSM) to coordinate data transfer between the UART and the matrix multiplication module.
- Use BRAM modules as temporary storage buffers for both input matrices and the resulting calculation.
- Dual-port BRAM is suggested for handling the 8-bit inputs while maintaining access for the processing unit.
- The UART Rx and Tx modules must be synchronized with the BRAM through control signals to indicate when data transfer is complete.
My project involves performing matrix multiplication in vhdl. The two input matrices (8 bits each) are sent using a terminal and received via UART Rx. The FPGA device receives data and operates (add or mult) on the two matrices and sends back the output (16) using the UART Tx and the output matrix is shown on the terminal. I am still in the design process.
1) How to input the matrix for multiplication or addition using the terminal?
2) How to use the BRAMs to receive the two matrices for the terminal?
3) Since I don't need to initialize BRAMs from an external file, how do I make it recieve data using the UART?
What is your FPGA experience ? Unless you want to use something like a Zynq you are going to need to do the following
1) Create a UART connected to a state machine which can download and upload the data over the terminal. The statemachine tells the MM module when the download has completed. e.g. you have recieved two 8 bit numbers.
2) Create the matrix multiplication module which performs the actual fucntion
3) write the data back into in the BRAM and tell the statemachine you have anew result to send out over the UART
This should be fairly straight forward to acheive. is it a homework project?
Thank you for responding.
I am fairly new to FPGAs.
This is a homework project and I am using a Basys 3 board.
- Does the BRAM solely work as a fifo when receiving and sending data?
- Should I use a Synchronous Dual port BRAM for receiving 8 bit inputs matrices?
- Do I need to make the BRAM (for ouput) send data directly to the UART Tx?
I have planned to make vhdl modules for the following: uart rx, uart tx, synchronous_bram (for input matrices), simple dual port bram(for result matrix) and a matrix-op unit.
How and where do I implement the FIFO with bram? Does the state machine go inside the bram inference modules?
