fpga spartan 6 io ports are no longer working
Started by 7 years ago●2 replies●latest reply 7 years ago●120 viewsA user is troubleshooting a Spartan-6 FPGA where I/O pins remain unresponsive or stuck at specific voltage levels despite successful JTAG programming. The discussion focuses on verifying the hardware environment and simplifying the design to isolate whether the issue is a physical failure or a configuration error.
- Verify that all power rails, including Core, Auxiliary, and I/O voltages, are correctly connected per the device schematic.
- Test with the simplest possible code, such as driving a single static output high, to eliminate logic errors.
- Confirm that pin assignments in the FPGA editor match the physical board layout and check for critical warnings during synthesis.
- Use a slow clock or counter to toggle an LED to verify that the internal logic and clock source are functioning correctly.
HELLO there,
i have spartan 6 of the familyxlc9 but i am facing a severe problem with it . first i can burn successfully with jtag on it .its power is okay but the problem is whatever code i am burning to it
the io ports values doesn't change always all the pins are zeros except 4 pins that have values between 0.9 and 1.2 and another pin that have 3.3 .although the code is working on xillinx it is a simple code. trying to output ones on all the pins i changed the code to a code that does nothing like the fpga sends the same values on the output pins . i thought that those pins are no longer working
changed to another pins but all are zeros . it is like the output ports keeps a certain previous state and stand still.
i don't know does my fpga fails and has to be changed ? although jtag is burning code successfully
does spi flash memory is not working ? although i tried to upload the code on fpga directly and get the same output
thanks in advance
Debugging this sort of thing is hard, especially remotely. So I just offer a series of possibilities in the hope they trigger something useful :)
I hope you have at least one LED on a user-controlled IO.
* Try the simplest possible code: an entity with 1 output pin and a single line of code that sets it to '1'. so something like (syntax not totally accurate as I'm hacking this in a sports hall without a proper editor)
entity e port (testpin: out std_logic); end;
architecture a1 of e is begin testpin <= '1'; end;
* Fix any errors or critical warnings. There are some errors that will not stop the tools producing a bitstream.
* Is the pinout correct - check in the FPGA editor that the pins you think should be wiggling are on the pin numbers you think they are.
Do nothing else until this works then
* Follow this up with the use of a clock to toggle pins on and off at 1 Hz.
* then a shift register that lights up the pins in order
You shouldn't need SPI flash working for this - just load the code over JTAG.
Please Check in the schematic if all VDDs and GNDs are connected to appropriate levels for the particular part - Core voltage, Auxiliary voltage, IO voltage etc.. Then do a thorough check of all IO assignments against IOs in use as in the board schematic - Dedicated Pins, NC pins etc.. Other things could be checked how many are in the daisy chain etc.. If any LED is connected, make a counter inside and see if you could toggle it. That would give confidence.
