Kenny Millar (@SpiderKenny)
I just found this fantastic youtube primer on getting to grips with the Arty platform (Xilinx Artix and Spartan 7-Series FPGAs)Whilst it doesn't teach HDL, it got...
Thanks again!I'd be more than happy to review your early versions etc. Yeah - for HDMI I don't intend to be decoding the raw HDMI signals myself, inside the FPGA,...
Thanks for your reply. I appreciate that.I don;t have any specific questions at the moment. I think mainly because I don't know what I don't know. If you see what...
Maybe I'm one of the worst people to be learning FPGAs because I've been a firmware developer on embedded CPUs and an application developer on Mac / Windows for...
Thanks for the reply! Much appreciated.I will look carefully at your suggestions - thank you!Some more info: The MachXO2 has a built in dedicated clock generator...
I have a pretty simple verilog project, in Lattice Diamond 3.11.My top module instantiates an OSCH (Lattice IP library) oscillator at 133 mhz, and a 'ws2812b' module...
@jt_eaton >We need to create an opensourced EDA tool chain using tools like kactus2 and have everyone support that.I would second that.
160 bits at 800 MHz - If my maths is correct, then that is about 800 x 1,000,000 x 160 which is 128 GBytes per second. Is that correct?This must be some pretty high-end...
@adamt99 - Thanks! This forum definitely seems to be full of kind and good natured people. It's a quite a marked difference to some of the others.
Thanks - your points are really good.Magic numbers! I should've know that. Thinking about it, it might be better if I allow the current clock speed to be expressed...
Hi This is one of the first verilog modules I wrote. It reads a 1-Wire iButton / Dallas keyfob code.The theory of operation is that approximately every two seconds...
@cfelton - Thanks for the reply.I think I might push my head above the parapet and post some verilog code of mine here for review!
I think that it's the limitation of the tools that make it so troublesome. Bob Zeidman in his book "Introduction to Verilog" seems very much in favour of schematic...
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