Why You Should be Using Python/MyHDL as Your HDL

Christopher Felton

Still RelevantIntermediate

Hardware Description Languages (HDLs) revolutionized the digital hardware design landscape when they were introduced 30 years ago. The majority of the complex digital hardware (IC and FPGA) - that has irreversibly changed our lives - was enabled by HDLs-mainly Verilog and VHDL. Although the mainstay HDLs have had much success, they haven't fundamentally changed since their inception. The defacto HDLs, Verilog and VHDL, have evolved over time, but this is good and bad. These languages have new features but some newer language constructs don't fit well with existing constructs - not a clean design. MyHDL strives to be an HDL based on proven concepts that can be powerful yet elegantly expressed (i.e. clean design)

Summary

This paper advocates using Python/MyHDL as an alternative HDL, showing how Python's language features enable cleaner, more modular RTL and how MyHDL can generate synthesizable Verilog or VHDL. Readers will learn practical benefits, trade-offs, and workflows for using MyHDL in FPGA and ASIC design flows.

Key Takeaways

Express RTL in Python/MyHDL to write more concise, testable, and modular hardware descriptions than equivalent Verilog/VHDL code.
Generate synthesizable Verilog or VHDL from MyHDL models to integrate with standard FPGA toolchains.
Prototype and verify designs faster by leveraging Python's simulation and unit-test ecosystems for testbench automation.
Integrate MyHDL models into existing flows, including co-simulation and toolchain handoff, while understanding limitations and synthesis caveats.

Who Should Read This

FPGA/ASIC engineers who know Verilog or VHDL and some Python, seeking faster prototyping, cleaner RTL design, and a path to generate Verilog/VHDL from high-level models.

Still RelevantIntermediate