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Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 8 years ago12 replieslatest reply 2 weeks ago2811 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Learning FPGA

Started by stephaneb 6 years ago18 replieslatest reply 10 hours ago4811 views
A few months ago, this community tackled the first FPGA FAQ titled When (and why) is it a good idea to use an FPGA in your embedded system design?.  Your contributions...

Variable IIR-Filter Coefficient calculation in frequency domain

Started by Nordmann 5 months ago6 replieslatest reply 2 months ago296 views
Hello,Currently im evaluating the usefulness of frequency domain filtering in FPGA for one of our projects. Im stuck with a problem that my limited knowledge of...
I own a Pynq Z1 FPGA board without built-in Wi-Fi. How can I connect a Wi-Fi module, specifically using GPIO or communication interfaces like UART, SPI, or I2C?...

dynamically configure Xilinx FFT IP core

Started by Amirtham 8 months ago1 replylatest reply 8 months ago76 views
Hi all,My design uses Xilinx's FFT LogiCORE IP which I use to do FFT of transform length 128 points. I configure the IP core in Vivado GUI, instantiate in my code...

Is N-body simulation in O(n) time possible?

Started by smjedison 9 months ago2 replieslatest reply 9 months ago81 views
Hi! My name is Mason. I've recently been messing around with FPGAs, and I think I found a way to do N-body simulation in O(n) time. First, some quick background....

Is this possible with an FPGA?

Started by Joe3502 4 years ago8 replieslatest reply 10 months ago223 views
Hi All, I am starting to learn Verilog in order to program FPGAs. I have a project where I need to take three digital signals coming from three hall sensors on...

LZW or BWC Compression cores for FPGAs

Started by Shparekh 1 year ago1 replylatest reply 11 months ago74 views
Hello,Can anyone recommend RTL level cores for LZW or BWC compression/decompresison engines? Thank you.Best regards,Sanjay 

Implementing a folded FIR on FPGA

Started by DHMarinov 3 years ago5 replieslatest reply 1 year ago179 views
Hello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...

Xilinx FIR Compiler Fractional Rate Converter

Started by ismailt42 4 years ago4 replieslatest reply 1 year ago346 views
Hello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...

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