Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 7 years ago14 replieslatest reply 1 month ago2474 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Is this possible with an FPGA?

Started by Joe3502 4 years ago8 replieslatest reply 3 weeks ago127 views
Hi All, I am starting to learn Verilog in order to program FPGAs. I have a project where I need to take three digital signals coming from three hall sensors on...

LZW or BWC Compression cores for FPGAs

Started by Shparekh 7 months ago1 replylatest reply 4 weeks ago45 views
Hello,Can anyone recommend RTL level cores for LZW or BWC compression/decompresison engines? Thank you.Best regards,Sanjay 

Implementing a folded FIR on FPGA

Started by DHMarinov 3 years ago5 replieslatest reply 7 months ago119 views
Hello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...

Xilinx FIR Compiler Fractional Rate Converter

Started by ismailt42 3 years ago4 replieslatest reply 7 months ago155 views
Hello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...

Noise Generated using differential pmods as single ended

Started by abdul_samad 4 years ago1 replylatest reply 7 months ago59 views
HiI have a zedboard and a nexys video artix 7 board. I am generating a sinusoid from DDS Core of the same frequency (by supplying the same phase increment and the...

Using a single DSP48E2 Slice to infer three 48-bit inputs adder

Started by learni 4 years ago1 replylatest reply 7 months ago176 views
Hi All,I have nine 8-bit values that I want to add using the dsp slices.As an example I tried this code from the Xilinx answer records(

LVDS as a comparator

Started by Tanu3 4 years ago1 replylatest reply 7 months ago129 views
I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal...

Lattice FPGA timing constraint help

Started by dave94024 3 years ago5 replieslatest reply 7 months ago242 views
I have an application using a Lattice UltraPlus FPGA which is mostly working except for some marginal behavior.  I'm pretty sure it's due to timing constraint issues...

Aldec Active-HDL vs Modelsim PE state of play.

Started by glenenglish 2 years ago3 replieslatest reply 7 months ago167 views
What's the state of play here  in 2021 ? I have had a Modelsim PE seat in maintenance for 16 years. Modelsim has not changed, improved any done anything in that...

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