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Hello, I am new to FPGA. I have seen a template in DE0-nano. I would like to display the value in "PWM_width <= PWM_width[5:0]+ PWM_adj;" one by one in a screen...
I have Nexys4 FPGA , it has a system clock of 100mhz, can it generate 200mhz clock, when using Clocking Wizard IP?
I'd like to use Vivado in non-project mode, using makefiles and Tcl scripts. However, my chip is a Zynq-7000 SoC where Vivado needs to generate a module representing...
Started by Trying to solve the following contradiction about "set_multicycle_path"case 1: "Vivado using constraints" pdf states that for most cases of timing relaxing multicycle...
Hello guys,I have been trying to implement to implement the SHA256 algorithm on my ARTY A7 35t using VivadoI am using TeraTerm to send information to the board...
Doubt about constraining external input
Started by 5 years ago●4 replies●latest reply 5 years ago●172 viewsHi all,I am usig an AD9914 DDShttps://www.analog.com/media/en/technical-documentation/data-sheets/AD9914.pdfwith its DROVER output connected to a I/O of the FPGA...
Efficient implementation of FIR filters on a FPGA
Started by 5 years ago●2 replies●latest reply 5 years ago●191 viewsHello there,I made a short video in which I present a way to implement FIR filters on FPGA (Xilinx) by using only DSP slices. You can check it out here: PS:I'd...
Polyphase Filter Bank channelizer issue
Started by 6 years ago●5 replies●latest reply 6 years ago●1413 viewsHello, I am currently studying the implementation of a Polyphase Filter Bank channelizer designed by Xilinx in its XAPP1161. The architecture is composed by a single...
UART communication For Nexys A7-100t
Started by 6 years ago●1 reply●latest reply 6 years ago●1462 viewsHello,I'm new to UART for FPGA and recently I tried a demo project that I found at: https://www.fpga4fun.com/SerialInterface.htmlMy problem is using RxD_data_ready...
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