Anatoliy Sergiyenko (@asser)
I`ve resolved such a problem in the following project:https://opencores.org/projects/fft_fir_filterIt contains a detailed description.
Altera FPGAs are not intended for the military applications.However, they are relatively cheap. For this reason, they are widely used in Russian armament.On the...
Today, the Cortex-m4 microcontrollers and similar ones have a speed up to approx. 100 MFLOPS. It`s enough to perform any real-time sound filtering.Such a chip...
90 DSP48 units of this FPGA are enough to implement a lot of DSP algorithms.But you would rather implement the filters and FFT in the sequential-parallel manner.When...
Really, gain is 5 bits. But in conditions when the signal has not the DC component. If you needn't such a gain you can truncate the resulting bit width to the desired...
The synthesis tool usually doesn't need the clock frequency at all. But one of the synthesis result is the maximum frequency which provides this design. It is estimated...
The RTL design paradigm insists that any device must have a clock signal wire and all registers are feeded by it writing the information by the clock edge.So, any...
Video stream compressor.At present, many old compression method patents are expired,and these methods may be freely implemented in FPGA.Consider GIF.
Usually, the pink noise is derived from the white noise by the filtering.Build the white noise generator based on LSFR, and attach to its output some band pass...
A-law is an algorithm of the log compression of the audio signals.It attracts for its simplicity. But it works bad for other data compression.You need other kind...
There is a special kind of filters called the minimum phase filters.They have unlinear phase characteristic but their group delay is minimized. For example, if a...
the operator '<=' is overloaded for any type of the signal.But the left and right sides must be of the equal type or be subtype of this type.You can assign the...
The up conversion filter is calculating the input sequence, which is split by zeros. Therefore, the output results are divided by 2 if the conversion is made up...
In such a situation, I usually use something like perl script to generate the vhdl text with the matrix content. (Perl can be built in the simulator). But in modelling,...
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