Adam Taylor (@adamt99)

Throughout his career Adam has used FPGA’s to implement a wide variety of solutions from RADAR to safety critical control systems, with interesting stops in image processing and cryptography along the way. He has a real love for FPGA and Engineering, in 2007 he started writing about FPGA’s, examining how to use them in different applications, techniques and processes. This developed most recently into his epic blog hosted by Xilinx on the Xcell Daily blog which contains over 100 instalments focusing upon how to use the Xilinx Zynq SoC based around the Microzed

Re: FPGA Clocking

Reply posted 2 years ago (03/04/2022)
Yes if you set up the Clocking wizard correctly it can, just set the clock out to 200Mhzit is really quite simple to do

Re: Does anyone have experience in RFSoCs?

Reply posted 4 years ago (04/21/2020)
I have a ZCU111, take a look at PYNQ.io there are a number of overlays for the RFSoC and creating your own is not too difficult. 

Re: recovery/removal violations, does it always matter?

Reply posted 5 years ago (06/08/2019)
The transition is caused by the reset signal being released in the set up / hold period of the flip flop, not due to the input transitioning in that same window. It...

Re: recovery/removal violations, does it always matter?

Reply posted 5 years ago (06/08/2019)
The simplest way it can cause an issue is by causing metastability in flip flops if the reset is removed too close to the active edge of the clock. Of course depending...

Re: VHDL Matrix Multiplication using UART and BRAM

Reply posted 6 years ago (06/30/2018)
What is your FPGA experience ? Unless you want to use something like a Zynq you are going to need to do the following 1) Create a UART connected to a state machine...

Re: Currently at Embedded World

Reply posted 6 years ago (02/28/2018)
I am on the Aristos stand if you want to swing by and say hello

Re: If FPGAs didn't work we won't be here?

Reply posted 7 years ago (12/30/2017)
This is an area I can help you with having designed a few FPGA for space and other SIL 4 applications along with many more commercial applications.They do work right...

Re: Greatest Conferences?

Reply posted 7 years ago (12/24/2017)
Conferences are very tricky in my view to get right, you need to demonstrate to the management of engineering companies why they need to send their employees.The...
The skill of an engineer is selecting the right tool for the right job, and not just selecting a FPGA for FPGA's sake. FPGA and the more recent heterogeneous system...

Re: Unlimited display on the board

Reply posted 7 years ago (08/15/2017)
Hi I do not know much about the Z Turn board however it has a HDMI output which is connected to the PL of the FPGA there are several IP cores which are free with...

Re: FPGA - ML & DL

Reply posted 7 years ago (08/15/2017)
Hi you need to check out the xilinx reVision and RAS stacks both support machine learning from Caffe Adam

Re: sampling 800mbps data in virtex 5QV

Reply posted 7 years ago (03/01/2017)
You may also be interested in this linkhttps://forums.xilinx.com/t5/Xcell-Daily-Blog/How-...

Re: sampling 800mbps data in virtex 5QV

Reply posted 7 years ago (03/01/2017)
The seven series devices are not space qualified at the moment hence the need for v5qv part. It is possible i have used v5qv and 3 gsps adc and dac but need careful...

Re: sampling 800mbps data in virtex 5QV

Reply posted 7 years ago (02/28/2017)
I have designed several space fpga including the v5 you need to think about Adc choice what is the output format 760 MHZ fs is 360 MHZ of bandwidth to be processed....

Re: VGA signal generation

Reply posted 8 years ago (12/26/2016)
Hi it is possible, you might want to check out http://adiuvoengineering.com/?p=23 for how to create the vga pattern. The rest of it is just simple logic.You will...

Re: manipulation of two dimensional matrices in VHDL

Reply posted 8 years ago (10/12/2016)
What fpga are you targeting? If it is spartan 6, seven series or later i would use the free HLS in C and use the matrix manipulation libraries. You can then use...

Re: Mealy or Moore? none and not even state machine

Reply posted 8 years ago (09/30/2016)
Hi Kaz,From what you have described above and in your reply to Chris below I would suggest that you re visit the use of state machines if you are using them for...
wlarsen If you have all HDL files in verilog or VHDL you can just write a top level file which performs the instantiation and port mapping (to use VHDL terms) and...
cfelton is correct this is definitely a layout issue, having done some high speed parallel buses at near the speeds you mention you will carefully need to consider...
@SpiderKenny I am sorry that you have come across that, I always try and help newbies and experienced engineers alike if I can. I work on the idea that I never...
Chris, I tend to agree I have a love hate relationship with the Vivado block diagram editor. A graphical top level can be very useful for creating the architecture,...

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