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Xilinx FIR Compiler Fractional Rate Converter
Started by 5 years ago●4 replies●latest reply 3 years ago●676 viewsHello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...
Noise Generated using differential pmods as single ended
Started by 6 years ago●1 reply●latest reply 3 years ago●146 viewsHiI have a zedboard and a nexys video artix 7 board. I am generating a sinusoid from DDS Core of the same frequency (by supplying the same phase increment and the...
Using a single DSP48E2 Slice to infer three 48-bit inputs adder
Started by 6 years ago●1 reply●latest reply 3 years ago●488 viewsHi All,I have nine 8-bit values that I want to add using the dsp slices.As an example I tried this code from the Xilinx answer records(https://www.xilinx.com/support/answers/66429.html).I...
I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal...
Lattice FPGA timing constraint help
Started by 6 years ago●5 replies●latest reply 3 years ago●1030 viewsI have an application using a Lattice UltraPlus FPGA which is mostly working except for some marginal behavior. I'm pretty sure it's due to timing constraint issues...
Aldec Active-HDL vs Modelsim PE state of play.
Started by 4 years ago●3 replies●latest reply 3 years ago●652 viewsWhat's the state of play here in 2021 ? I have had a Modelsim PE seat in maintenance for 16 years. Modelsim has not changed, improved any done anything in that...
Hello everyone!I am trying to implement Raised-cosine filter in VHDL. In the current simulation I am using the standard method of the filter simulation:- create...
FPGA speed and timing closure metrics
Started by 4 years ago●3 replies●latest reply 3 years ago●143 viewsWe have plenty data sheets, documents, forum replies and videos on various fpgas and designs. However what is missing in all cases is some idea how fast can one...
Started by I am a complete beginner when it comes to FPGA so any advice would be helpful.I have been looking at updating my audio system which currently takes an analogue...
FPGA - how to receive and use external trigger
Started by 3 years ago●1 reply●latest reply 3 years ago●134 viewsAppreciate any specific help or general guidance to my question below:Suppose I have two FPGAs: FPGA_master and FPGA_slave.On FPGA_master I can generate an internal...
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