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Started by Hello,I am beginner in Spartan 3A DSP Video Starter Kit. I wish to implement an algorithm which takes Composite Video input at 640x480@25Hz (PAL720) and outputs...
Generating a Block Design in Vivado from existing Verilog & IP files
Started by 8 years ago●2 replies●latest reply 8 years ago●6803 viewsI have a #Vivado project that I pieced together from #Verilog and IP files from a Github repository. I believe the project was originally created in ISE as there...
Code review. Newbie's first verilog module!
Started by 8 years ago●4 replies●latest reply 8 years ago●346 viewsHi This is one of the first verilog modules I wrote. It reads a 1-Wire iButton / Dallas keyfob code.The theory of operation is that approximately every two seconds...
Best method for a large dot vector
Started by 9 years ago●13 replies●latest reply 9 years ago●126 viewsI am trying to compute a 274 sample dot vector in an FPGA (in #Verilog). I have the clock cycles to compute it over many clocks, but I am having trouble meeting...
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