Hello,I am beginner in Spartan 3A DSP Video Starter Kit. I wish to implement an algorithm which takes Composite Video input at 640x480@25Hz (PAL720) and outputs...

Generating a Block Design in Vivado from existing Verilog & IP files

Started by wlarsen 8 years ago2 replieslatest reply 8 years ago6627 views
I have a #Vivado project that I pieced together from #Verilog and IP files from a Github repository. I believe the project was originally created in ISE as there...

Code review. Newbie's first verilog module!

Started by SpiderKenny 8 years ago4 replieslatest reply 8 years ago331 views
Hi This is one of the first verilog modules I wrote. It reads a 1-Wire iButton / Dallas keyfob code.The theory of operation is that approximately every two seconds...

Best method for a large dot vector

Started by garengllc 8 years ago13 replieslatest reply 8 years ago123 views
I am trying to compute a 274 sample dot vector in an FPGA (in #Verilog).  I have the clock cycles to compute it over many clocks, but I am having trouble meeting...

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