Hello there,

This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.
You can check it out here: https://youtu.be/LD8176BYne8

Cheers!

Thanks,

Just pointing out that your video about manual dsp based design is intuitive for study and beginners. some minor issues with pre-adder: it increases data width by one bit at multiplier input (not a problem here). polyphase subfilters for upsampling will also lose symmetry and so preadder will not apply.

In actual industry we use ip core for filter and forget about manual design as it is quicker. after all we do a lot of ip based work that come at no extra license cost.

I will not say same for sysgen as it is a bit complicated platform but ip cores can do whatever structure is best for fpga target.

Hi kaz,

I'll take a look at the polyphase filters and the more high-level approaches later on.

You certainly mean "designing the filter is done more quickly".

Well, I do it that way that I drop my native VHDL into the design and use my Excel to obtain the filter's Coeffs and optimize vector sizes automatically including dithering and rounding typically beating the Core-Gen's outputs regulary :-)

First time I hear spread sheet dsp beats ip people. Congrats

Show me a working core where statistical and optimized truncation by rounding is performed automatically (and correctly) while calculating the physical constraints such as the definition and value range, the measurement uncertainty and the meaningful resolution derived from them.  Just give it to me. The whole thing should be done in such a way that the parameters can also be inserted from the specification within seconds and the result is available without having to think about it, formulate it and then check it by simulation. Oh yes, and please don't forget the application-specific noise profile. :-)

Seriously: If MATLAB, Xilinx and CoreGEn could always build what I need, I would not have programmed it myself :-)