Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm
Michael Morris presents a practical, FPGA-friendly fixed-point implementation of the Goldschmidt algorithm to compute sqrt and 1/sqrt. The post shows how an msb-indexed Y_est table and an N_adj scaling factor produce a reliable initial inverse-square-root estimate for an FP32B16 format, enabling five-iteration convergence. It also covers fixed-point normalization, multiplier/shift tradeoffs, and why this fits a real-time motion-controller use case.
Cutting a Path Forward
As a software developer building a drone navigation prototype, the author turned to FPGAs after realizing CPUs and cloud tethering break the "simple, cheap, reliable" constraints. He proposes mapping sensor probabilities into a graph-cut network using negative log-likelihoods to produce risk‑averse, real‑time path planning, aiming for tens of milliseconds. The post explains the graph-cut idea, cites FPGA precedents, and lays out a practical FPGA-focused plan of attack.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm
Michael Morris presents a practical, FPGA-friendly fixed-point implementation of the Goldschmidt algorithm to compute sqrt and 1/sqrt. The post shows how an msb-indexed Y_est table and an N_adj scaling factor produce a reliable initial inverse-square-root estimate for an FP32B16 format, enabling five-iteration convergence. It also covers fixed-point normalization, multiplier/shift tradeoffs, and why this fits a real-time motion-controller use case.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
Cutting a Path Forward
As a software developer building a drone navigation prototype, the author turned to FPGAs after realizing CPUs and cloud tethering break the "simple, cheap, reliable" constraints. He proposes mapping sensor probabilities into a graph-cut network using negative log-likelihoods to produce risk‑averse, real‑time path planning, aiming for tens of milliseconds. The post explains the graph-cut idea, cites FPGA precedents, and lays out a practical FPGA-focused plan of attack.
Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm
Michael Morris presents a practical, FPGA-friendly fixed-point implementation of the Goldschmidt algorithm to compute sqrt and 1/sqrt. The post shows how an msb-indexed Y_est table and an N_adj scaling factor produce a reliable initial inverse-square-root estimate for an FP32B16 format, enabling five-iteration convergence. It also covers fixed-point normalization, multiplier/shift tradeoffs, and why this fits a real-time motion-controller use case.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
Cutting a Path Forward
As a software developer building a drone navigation prototype, the author turned to FPGAs after realizing CPUs and cloud tethering break the "simple, cheap, reliable" constraints. He proposes mapping sensor probabilities into a graph-cut network using negative log-likelihoods to produce risk‑averse, real‑time path planning, aiming for tens of milliseconds. The post explains the graph-cut idea, cites FPGA precedents, and lays out a practical FPGA-focused plan of attack.
