Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
