A Bit Bucket had Holes
Christopher Felton looks back at TierLogic's multi-layer FPGA idea and its recent shutdown, contrasting it with Tabula's virtual 3D approach. He asks whether physical-layer stacking could have delivered the ultra-high logic density some designs need, especially at modest clock rates and small footprints. The post highlights how funding, market fit, and patent outcomes often decide whether neat FPGA tech becomes a product.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Holy Bit Bucket
Christopher Felton reacts to Tabula's 'Spacetime' pitch, which claims an 8x boost in LUT density by time-division multiplexing internal logic. He urges caution, comparing Tabula to Achronix and pointing out that early parts will likely target high-end networking and carry premium pricing. The post argues inexpensive development boards will be crucial for wider adoption.
The Spartans
Christopher Felton walks through the Spartan6 FPGA basics, explaining CLBs, slices, and the new 6-input LUTs while comparing them to Spartan3. He ran timing-driven mappings of real gateware to show practical LUT utilization differences. The post gives a pragmatic estimate of expected LUT savings and points out where mapping results can vary depending on the design.
Summer of gateware is coming (again)
Wondering what gateware will come out of this summer? Christopher Felton announces MyHDL is back in Google Summer of Code and has been awarded six student slots. Projects span GEMAC, a Leros tiny processor, JPEG encoder front/backends, RISC-V tooling and HDMI+RISC-V work. Follow along for short project updates and a final summer summary.
What do Ohio, Python, and FPGAs have in common?
Christopher Felton is bringing MyHDL, Python, and hands-on FPGA work to the free pyohio regional conference on July 27-28. His informal talk introduces programmable hardware to imperative thinkers, contrasts FPGAs with modern computers, and showcases the MyHDL package. The follow-up workshop lets Python programmers edit an example, configure a Xess development board, and see their changes run on real hardware.
A Bit Bucket had Holes
Christopher Felton looks back at TierLogic's multi-layer FPGA idea and its recent shutdown, contrasting it with Tabula's virtual 3D approach. He asks whether physical-layer stacking could have delivered the ultra-high logic density some designs need, especially at modest clock rates and small footprints. The post highlights how funding, market fit, and patent outcomes often decide whether neat FPGA tech becomes a product.
MyHDL @EDAPlayground
MyHDL just got easier to try: it's available on EDAPlayground, so you can run Python-based HDL verification directly in the browser. The two-panel editor places the testbench on the left and the HDL under test on the right, with public examples such as a simple strobe and a RAM test ready to copy. Christopher Felton also links a curated resource list to help you get started quickly.
Summer of Gateware
Christopher Felton walks through MyHDL's first year as a Google Summer of Code sub organization, from selecting two students to shipping SDRAM and conversion work. He highlights the practical bumps, including proposal expectations, the value of early patches, and the need for frequent mentoring and flexible milestones. The post shares concrete lessons for mentors, students, and projects planning to participate in GSoC.
MyHDL @EDAPlayground
MyHDL just got easier to try: it's available on EDAPlayground, so you can run Python-based HDL verification directly in the browser. The two-panel editor places the testbench on the left and the HDL under test on the right, with public examples such as a simple strobe and a RAM test ready to copy. Christopher Felton also links a curated resource list to help you get started quickly.
A Bit Bucket had Holes
Christopher Felton looks back at TierLogic's multi-layer FPGA idea and its recent shutdown, contrasting it with Tabula's virtual 3D approach. He asks whether physical-layer stacking could have delivered the ultra-high logic density some designs need, especially at modest clock rates and small footprints. The post highlights how funding, market fit, and patent outcomes often decide whether neat FPGA tech becomes a product.
Holy Bit Bucket
Christopher Felton reacts to Tabula's 'Spacetime' pitch, which claims an 8x boost in LUT density by time-division multiplexing internal logic. He urges caution, comparing Tabula to Achronix and pointing out that early parts will likely target high-end networking and carry premium pricing. The post argues inexpensive development boards will be crucial for wider adoption.
