[Comments] C HLS Benefits

Christopher FeltonApril 11, 20142 comments

Earlier this week I posted a small write-up comparing a hardware median calculation implemented in a C-to gates "HLS" (Vivado C HLS) and a version in MyHDL.  For a long time I have had the belief that C-to-gate technologies are of little to no benefit - based on the simple premise that "C" is not that high-level of a language (I actually consider it lower than Verilog and VHDL ... but that is a conversation for another time).

Language comparisons are always difficult (to impossible).  In the post there are two features being compared, the language design and the language abstraction level:

The "C" language with the HLS pragmas
Imperative description [1]

The Python language with the MyHDL package
Concurrent/Simulation description

In the comparison the above are mashed together but there is no good way to separate them, you would need imperative HLS synthesis and simulation RTL synthesis in the same language (a multi-paradigm language, not comparing syntax and design but paradigms/descriptions).

The use of MyHDL is important in this case.  MyHDL is essentially at the same abstraction level of Verilog and VHDL but it simplifies the concurrent description, benefits from the Python design philosophy (simplicity, readability, etc.), and has a full featured elaboration phase.

If the comparison was made with Verilog or VHDL (C*) it might seem like there is a benefit to the "C" description because of clunkiness in the V* languages (which is different than the abstraction level of the language).  From my point of view the comparison was successful - it shows little to no benefit to the "C" version for the particular example.  I will be following up the post with the rest of the median filter implementation shortly (ahh shortly is relative).

Obviously, if you know "C" really well and want to do FPGA development and do not want to learn another language "C" based tools might be some benefit because you do not have to learn a new language.  But there are all kinds of drawbacks and my guess is majority of developers developing massive parallel implementations (e.g. FPGA) know more languages than "C" and would find greater utility in a non C-HLS tool.

[1] I call it an imperative description because it is a list of steps with some structure, e.g. the loops. Many would consider this structured code and "C" is typically considered procedural.  Both procedural and structured are imperative.  I use imperative because it is general and commonly used.

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Comment by dstanforMay 1, 2015
I'm working up a comparison myself between HandelC and myHDL. I know HandelC better than python or myhdl, so myhdl has a disadvantage in the comparison which I'm trying to keep in mind to be fair. My plan is to implement a module in MyHdl that I already have in HandelC. My hypothesis is HandelC is 'faster' to write due to it's abstraction level, but MyHdl will be easier to test since our hardware acceptance tests are already in python.
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Comment by cfeltonMay 1, 2015
Sounds interesting, if you want any help and / or opinions on the MyHDL implementation I am willing to review it.

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