A Bit Bucket had Holes
Christopher Felton looks back at TierLogic's multi-layer FPGA idea and its recent shutdown, contrasting it with Tabula's virtual 3D approach. He asks whether physical-layer stacking could have delivered the ultra-high logic density some designs need, especially at modest clock rates and small footprints. The post highlights how funding, market fit, and patent outcomes often decide whether neat FPGA tech becomes a product.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Holy Bit Bucket
Christopher Felton reacts to Tabula's 'Spacetime' pitch, which claims an 8x boost in LUT density by time-division multiplexing internal logic. He urges caution, comparing Tabula to Achronix and pointing out that early parts will likely target high-end networking and carry premium pricing. The post argues inexpensive development boards will be crucial for wider adoption.
The Spartans
Christopher Felton walks through the Spartan6 FPGA basics, explaining CLBs, slices, and the new 6-input LUTs while comparing them to Spartan3. He ran timing-driven mappings of real gateware to show practical LUT utilization differences. The post gives a pragmatic estimate of expected LUT savings and points out where mapping results can vary depending on the design.
Holy Bit Bucket
Christopher Felton reacts to Tabula's 'Spacetime' pitch, which claims an 8x boost in LUT density by time-division multiplexing internal logic. He urges caution, comparing Tabula to Achronix and pointing out that early parts will likely target high-end networking and carry premium pricing. The post argues inexpensive development boards will be crucial for wider adoption.
Are you kidding me?
Christopher Felton pushes back on the idea that C/C++/SystemC are the natural path to higher-abstraction FPGA design. He argues hardware designers often do not use C-family languages for modeling and simulation, so choosing C as the HLS lingua franca may be more about tool momentum than suitability. The post urges reconsidering languages with higher abstraction and lower cost of entry for system modeling and HLS.
MyHDL ... MyPWM
Christopher Felton presents a compact MyHDL PWM engine designed to be configured at design time and targeted for FPGA synthesis. The module derives PWM bit width from the system clock frequency and desired pwm_frequency, truncates inputs when necessary, and prints parameter summaries for different clock/pwm combinations. The post includes the full MyHDL source and a simulation waveform showing the input signal and the modulated output, making it easy to reproduce.
A Bit Bucket had Holes
Christopher Felton looks back at TierLogic's multi-layer FPGA idea and its recent shutdown, contrasting it with Tabula's virtual 3D approach. He asks whether physical-layer stacking could have delivered the ultra-high logic density some designs need, especially at modest clock rates and small footprints. The post highlights how funding, market fit, and patent outcomes often decide whether neat FPGA tech becomes a product.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
Summer of Gateware
Christopher Felton walks through MyHDL's first year as a Google Summer of Code sub organization, from selecting two students to shipping SDRAM and conversion work. He highlights the practical bumps, including proposal expectations, the value of early patches, and the need for frequent mentoring and flexible milestones. The post shares concrete lessons for mentors, students, and projects planning to participate in GSoC.
A Bit Bucket had Holes
Christopher Felton looks back at TierLogic's multi-layer FPGA idea and its recent shutdown, contrasting it with Tabula's virtual 3D approach. He asks whether physical-layer stacking could have delivered the ultra-high logic density some designs need, especially at modest clock rates and small footprints. The post highlights how funding, market fit, and patent outcomes often decide whether neat FPGA tech becomes a product.
Holy Bit Bucket
Christopher Felton reacts to Tabula's 'Spacetime' pitch, which claims an 8x boost in LUT density by time-division multiplexing internal logic. He urges caution, comparing Tabula to Achronix and pointing out that early parts will likely target high-end networking and carry premium pricing. The post argues inexpensive development boards will be crucial for wider adoption.
