How to do Math's in FPGA - Using VHDL 2008

Adam Taylor

Following the introduction of VHDL 93, which introduced the numeric_std package and the signed and unsigned types, implementing fixed point maths has been fairly straight forward. Using this package, we can implement mathematics using a fixed point representation. However, to implement a fixed point algorithm we need to understand the simple rules regarding fixed point operations.

Why You Should be Using Python/MyHDL as Your HDL

Christopher Felton

Hardware Description Languages (HDLs) revolutionized the digital hardware design landscape when they were introduced 30 years ago. The majority of the complex digital hardware (IC and FPGA) - that has irreversibly changed our lives - was enabled by HDLs-mainly Verilog and VHDL. Although the mainstay HDLs have had much success, they haven't fundamentally changed since their inception. The defacto HDLs, Verilog and VHDL, have evolved over time, but this is good and bad. These languages have new features but some newer language constructs don't fit well with existing constructs - not a clean design. MyHDL strives to be an HDL based on proven concepts that can be powerful yet elegantly expressed (i.e. clean design)

Rapid Prototyping of Embedded Video Processing Systems in FPGA Devices

Andrej Trost, Andrej Žemva

Design of video processing circuits requires a variety of tools and knowledge, and it is difficult to find the right combination of tools for an efficient design process, specifically when considering open tools for evaluation or educational purpose. This chapter presents an overview of video processing requirements, programmable devices used for embed? ded video processing and the components of a video processing chain. We propose a novel design flow for generating customizable intellectual property (IP) cores used in streaming video processing applications. This design flow is based on domain-specific modules in Python language. Examples of generated cores are presented.

High Level Synthesis Tool for High Speed Packet Processing

Yian Wang, Venkata Soumya Pakki

The main objective of this Master Thesis is to design and implement a high level synthesis tool for high speed packet processing. For a given network packet, determining the destination and performing the required alterations to the packet are the key parts of Packet Processing. The idea is to provide customers a customized Ethernet switch which is reliable and flexible. As a requirement for this, a high level packet processing language (PPL) is designed instead of any hardware descriptive language because of the regularity of packet processing. The packet processing is described in a powerful way based on the PPL. In this thesis, a design of Ethernet switch based on the PPL is proposed. Hardware implementation is done for the design and MyHDL is used as the hardware description language. Using Python, the compiled PPL program is translated into an hardware model. A tool has been developed which consists of a hardware generator and certain hardware infrastructures. Another part in the thesis is optimization of the initial design. For instance, optimization is done to run as much code as possible in parallel or for removal of unused hardware in the generated switch. Verification is done and synthesis results have been listed comparing the two designs. Hence, we conclude that the initial design is more flexible and has more redundancy while the optimized design is more friendly to hardware cost and power consumption.

Agile Testing on an Embedded Field Programmable Gate Array Platform

Todor Vlaev

Agile software methodologies are the state of art methodologies used on current software projects. Testing is one of the main pillars of agile development and many of the practices are common among various flavours of the methodologies. Despite their wide-spread adoption in different domains, agile testing practices still seem to be a novel concept on embedded programming projects. This is specifically true when it comes to hardware design modeling. Thus, the goal of this project was to introduce the main concepts of agile testing and demonstrate their application on an Field Programmable Gate Array (FPGA) platform. The project was conceptually divided into two parts. The first one was the design and implementation of an FPGA development board. The second part focused on developing hardware design modules with a suitable hardware description language and ultimately building a contained testing system to demonstrate the most important agile testing practices. The result of the first phase was a working FPGA development board and an Ethernet extension board. During the second phase example hardware models were designed with MyHDL. Unit tests were implemented before the actual modules, thus adopting a testdriven development (TDD) approach. The tests were automated with the help of a continuous integration server. A viable process for a functional testing routine was also outlined. Based on the outcomes, it can be concluded that agile testing practices can be successfully utilized even in the specific domain of digital design. The natural continuation of this project would be the implementation of the suggested functional testing routine.

Implementing the Nintendo Entertainment System on a FPGA

Jonathan Sieber

In this work I try to implement the Nintendo Entertainment System (NES) on a FPGA platform. The NES is one of the most famous video game consoles of the 8-bit era. Using custom designed hardware that was primarily optimized for low cost, and was not very powerful at that time, it still was the basis for a big library of high quality games, that are still fun to play today. Besides being a practical exercise in hardware design, this project aims to be a continuation of the efforts of the emulator scene, to conserve video game history by bringing it to new hardware platforms.

Accelerating Gauss-Newton Filters on FPGAs

Jean-Paul Costa da Conceicao

Radar tracking filters are generally computationally expensive, involving the manipulation of large matrices and deeply nested loops. In addition, they must generally work in real-time to be of any use. The now-common Kalman Filter was developed in the 1960's specifically for the purposes of lowering its computational burden, so that it could be implemented using the limited computational resources of the time. However, with the exponential increases in computing power since then, it is now possible to reconsider more heavy-weight, robust algorithms such as the original nonrecursive Gauss-Newton filter on which the Kalman filter is based[54]. This dissertation investigates the acceleration of such a filter using FPGA technology, making use of custom, reduced-precision number formats.

Introducing the Spartan 3E FPGA and VHDL

Mike Field

I want to help hackers take the plunge into the world of FPGAs-- Starting at purchasing an FPGA development board, and all the way through the process of getting their first project up and running. In this eBook, we will discuss the low level details of working with FPGAs, rather than diving straight into the System on a Chip (SOAC) level.

FPGAs for Dummies - Altera Special Edition

Andrew Moore

Field programmable gate arrays (FPGAs) are integrated circuits that enable designers to program customized digital logic in the field. FPGAs have been around since the 1980s and were originally conceived to give all design teams the ability to create custom logic. In the early days, using an FPGA in your design meant you had to do a lot of programming just to get your FPGA to perform simple functions, so most designers avoided them. If you haven’t looked into FPGAs since your university studies way back when, you’ll want to take another look at them. The FPGA has evolved from a useful but humble interface device into a system-level integrated circuit (IC) with its own microprocessors, memory blocks, and interfaces. It’s the next big thing. Now would be a great time to get an inexpensive development kit, download free tools, and begin to explore this world for yourself. And this book will help you understand the practical uses of FPGAs.

Embedded Design Handbook


The Embedded Design Handbook complements the primary documentation for the Altera® tools for embedded system development. It describes how to most effectively use the tools, and recommends design styles and practices for developing, debugging, and optimizing embedded systems using Altera-provided tools. The handbook introduces concepts to new users of Altera’s embedded solutions, and helps to increase the design efficiency of the experienced user.