FPGARelated.com

Why I would choose an FPGA development board?

Pablo TrujilloPablo Trujillo November 17, 20221 comment

FPGA boards are the smarter choice for hands-on learning and flexible hardware design. Compared with microcontroller dev boards, they let you run many hardware tasks in parallel, reuse the same HDL across different vendors, and even host soft-core microcontrollers inside the fabric. This post walks through those practical advantages and points out modern low-cost boards that make FPGAs accessible for students and engineers.


A New Related Site!

Stephane BoucherStephane Boucher September 22, 20224 comments

The post announces the launch of MLRelated, a new Related site dedicated to machine learning and deep learning. It positions MLRelated as complementary to existing Related sites by highlighting cross-cutting interests: TinyML for embedded developers, machine/deep learning applications in signal processing, and FPGA-based AI/ML implementations. The new site debuts with a modest amount of content and is expected to expand rapidly through contributions from the Related community in the form of blogs, forum threads, and webinars. The author invites readers to report navigation errors, share feedback, and propose ideas to help steer MLRelated into a practical, community-driven resource for researchers and practitioners in ML and adjacent domains.


The DSP Online Conference - Right Around the Corner!

Stephane BoucherStephane Boucher September 20, 2020

Three months after a forum post, Stephane Boucher and Jacob Beningo pulled together the DSP Online Conference, a two-day virtual event featuring 14 talks from leading DSP experts. Most sessions are 30 to 60 minutes with a 30-minute Zoom Q&A, while extended deep dives from speakers like fred harris are included. Registered attendees get one-year on-demand access, and free or reduced passes are available.


Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm

Michael MorrisMichael Morris June 14, 202010 comments

Michael Morris presents a practical, FPGA-friendly fixed-point implementation of the Goldschmidt algorithm to compute sqrt and 1/sqrt. The post shows how an msb-indexed Y_est table and an N_adj scaling factor produce a reliable initial inverse-square-root estimate for an FP32B16 format, enabling five-iteration convergence. It also covers fixed-point normalization, multiplier/shift tradeoffs, and why this fits a real-time motion-controller use case.


MyHDL synthesis: from browser to FPGA in five seconds

Martin StrubelMartin Strubel May 22, 2020

Martin Strubel walks through how modern open-source tooling slashes the pain of converting super-HDLs into FPGA-ready firmware. Instead of long translation chains from MyHDL or nMigen into Verilog or VHDL, yosys and its Python API let you build synthesizeable primitives on the fly, inspect schematics, and emit synthesized Verilog or firmware quickly. The post explains the shift from toolchain friction to fast browser-to-FPGA workflows.


Already 3000+ Attendees Registered for the Upcoming Embedded Online Conference

Stephane BoucherStephane Boucher February 14, 2020

More than 3,000 engineers have already signed up for the Embedded Online Conference, and free registration closes at the end of February. Stephane Boucher highlights four practical tracks—DSP and machine learning, FPGA, embedded systems programming, and embedded systems security—and notes that every talk will be available to stream on demand from May 20. If you prefer no-travel learning or want flexible access to world-class talks, register now.


Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers

Steve MaslenSteve Maslen June 18, 201917 comments

Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.


Free Goodies from Embedded World - Full Inventory and Upcoming Draw Live-Streaming Date

Stephane BoucherStephane Boucher March 22, 20191 comment

Stephane came back from Embedded World with a massive haul of development kits, tools and swag and decided to give it away to multiple winners. Read the full inventory, learn how to enter by liking or sharing the LinkedIn and Twitter posts, and tune in Friday March 29 at 1pm EST on EmbeddedRelated.tv for the live draw where winners will pick their prizes.


Free Goodies from Embedded World - What to Do Next?

Stephane BoucherStephane Boucher March 6, 20193 comments

Stephane Boucher went on a hunt for free stuff at Embedded World to assemble a giveaway bundle for a lucky reader. This short update shares that haul and asks the embedded community for ideas on what to do next. It is a conversational call for suggestions, aiming to turn conference swag into a useful prize.


Back from Embedded World 2019 - Funny Stories and Live-Streaming Woes

Stephane BoucherStephane Boucher March 1, 20191 comment

Stephane Boucher tried live-streaming multiple talks from Embedded World 2019 and turned a chaotic experiment into a useful set of lessons for embedded engineers. Between broken tripods, flaky venue WiFi, tricky German SIM purchases, and audio nightmares, he learned practical fixes for reliable streams and better video quality. Read this if you want candid, tactical advice on streaming hardware, connectivity, and on-site troubleshooting.


Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

Steve MaslenSteve Maslen November 22, 2018

A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.


VHDL tutorial - A practical example - part 1 - Hardware

Gene BrenimanGene Breniman May 18, 20111 comment

Gene Breniman walks through a practical CPLD-based data acquisition engine built for a low-power handheld instrument, focusing on hardware choices, signal flow, and pin assignments. The article explains component selection including a PCM1870 ADC, CY14B101Q2 serial nvSRAM, and an XC2C64A CPLD, and shows how the CPLD acts as an SPI sequencer and I2S clock master while minimizing microcontroller pins and power draw.


BGA and QFP at Home 1 - A Practical Guide.

Victor YurkovskyVictor Yurkovsky October 13, 20134 comments

It's a myth that BGAs and fine-pitch QFPs can't be soldered at home. Victor Yurkovsky lays out a practical, no-frills approach for hobbyists to design and assemble FPGA boards using 2-layer PCBs, breakout modules, and low-cost reflow methods like toaster ovens or hotplates. The article focuses on manufacturable PCB choices, netlist-driven workflows, and power/decoupling tactics that make high-density parts approachable for amateurs.


Linear Feedback Shift Registers for the Uninitiated, Part I: Ex-Pralite Monks and Finite Fields

Jason SachsJason Sachs July 3, 20176 comments

Jason Sachs demystifies linear feedback shift registers with a practical, bitwise view and the algebra that explains why they work. Readable examples compare Fibonacci and Galois implementations, show a simple software implementation, and reveal the correspondence between N-bit Galois LFSRs and GF(2^N) so you can pick taps and reason about maximal-length pseudorandom sequences.


Free Goodies from Embedded World - Full Inventory and Upcoming Draw Live-Streaming Date

Stephane BoucherStephane Boucher March 22, 20191 comment

Stephane came back from Embedded World with a massive haul of development kits, tools and swag and decided to give it away to multiple winners. Read the full inventory, learn how to enter by liking or sharing the LinkedIn and Twitter posts, and tune in Friday March 29 at 1pm EST on EmbeddedRelated.tv for the live draw where winners will pick their prizes.


Use DPLL to Lock Digital Oscillator to 1PPS Signal

Michael MorrisMichael Morris July 24, 20168 comments

Michael Morris demonstrates a practical DPLL that locks a Direct Digital Synthesizer to a GPS 1PPS signal, achieving sub-microsecond alignment and removing reference-oscillator frequency error. The design uses a Phase-Frequency Detector for 0 degree phase lock, a multiplier-free α-filter, and a limiter to prevent saturation, and includes coast and re-lock logic plus a synthesizable Verilog reference core.


I don’t often convert VHDL to Verilog but when I do ...

Christopher FeltonChristopher Felton December 24, 20142 comments

Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.


Using GHDL for interactive simulation under Linux

Martin StrubelMartin Strubel October 24, 2011

Martin walks through using the free GHDL VHDL simulator on Linux to go beyond static testbenches and run interactive simulations. You will see how GHDL and gtkwave give a fast, low-cost waveform workflow, how to call C code from VHDL via the VHPI interface, and how simple pipes let real software talk to your simulated FPGA for deeper system-level debugging.


VHDL tutorial - combining clocked and sequential logic

Gene BrenimanGene Breniman March 3, 2008

Need the ADC clock to sometimes be the raw 40MHz input? Gene Breniman shows how to extend a reloadable, counter-based VHDL clock divider to support a master-clock pass-through by using a conditional signal assignment to switch between the internal ADCClk and Mclk. The article also covers remapping ClkSel values and includes a working XC2C32A CPLD build that leaves room for future enhancements.


Free Goodies from Embedded World - What to Do Next?

Stephane BoucherStephane Boucher March 6, 20193 comments

Stephane Boucher went on a hunt for free stuff at Embedded World to assemble a giveaway bundle for a lucky reader. This short update shares that haul and asks the embedded community for ideas on what to do next. It is a conversational call for suggestions, aiming to turn conference swag into a useful prize.


Sensors Expo - Trip Report & My Best Video Yet!

Stephane BoucherStephane Boucher August 3, 20183 comments

Stephane Boucher turns a first-time Sensors Expo visit into a fun travelogue and a polished conference highlights video. He mixes candid trip anecdotes from Moncton to San Jose, electric-scooter discoveries, Santa Cruz detours, Airbnb tips, and on-the-floor expo footage. The post culminates in what he calls his best highlights reel yet, plus a follow-up video focused on embedded and IoT.


Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!

Stephane BoucherStephane Boucher May 29, 20186 comments

Stephane Boucher is heading to Sensors Expo in San Jose for the first time, and he is bringing cameras to capture demos and build a highlights video. He is also looking for roommates for a roomy Airbnb near the convention center, plus local tips for making the most of a free day in the Bay Area. If you are attending, there is also a registration discount code and a VIP pass giveaway in the mix.


Crowdfunding Articles?

Stephane BoucherStephane Boucher April 12, 201828 comments

Technical writers in the embedded world often have the expertise, but not always the time or incentive to turn it into a post. Stephane Boucher explores a crowdfunding model for technical articles, where readers would pledge small amounts to back promising abstracts before the writing begins. It is an interesting attempt to create more high quality EE content by paying authors upfront.


Embedded World 2018 - More Videos!

Stephane BoucherStephane Boucher March 27, 20181 comment

Two cinematic videos from Embedded World 2018 turn the show floor into slow-motion, stabilized footage using a Zhiyun Crane gimbal and a Sony a6300. One is a SEGGER booth highlights piece featuring Rolf Segger and Axel Wolf, the other is a roaming montage with appearances from Jacob Beningo, Micheal Barr, and Alan Hawse. Stephane asks viewers to enable audio and share feedback.


Embedded World 2018 - The Interviews

Stephane BoucherStephane Boucher March 21, 2018

Stephane Boucher brought video gear to Embedded World 2018 and teamed up with Jacob Beningo to capture concise vendor interviews that focus on real product news. The videos showcase Percepio's new Tracealyzer with a drone demo, Intrinsic ID's method for creating device-unique IDs from manufacturing variations, and SEGGER's broader toolset including embOS now certified by TÜV SÜD. Watch for short demos and expert explanations.


Finally got a drone!

Stephane BoucherStephane Boucher August 28, 20172 comments

Stephane Boucher finally bought a DJI Phantom 4 and found it does more than boost his video production value, it’s also hugely fun to fly. He used the drone for an aerial shot at SEGGER’s anniversary and for a beach project where kids drew a turtle while a separate camera captured a side timelapse. The post highlights creative shot combinations and a reminder to fly where it is legal.


SEGGER's 25th Anniversary Video

Stephane BoucherStephane Boucher July 18, 20172 comments

Stephane Boucher spent a week at SEGGER's headquarters and distilled that visit into a tight, two-minute 25th anniversary video. The post highlights rising production value, thanks to softbox lighting and a two-camera setup that allows seamless wide-to-tight cuts and emotional close-ups. Stephane invites readers to watch full screen, leave feedback and thumbs-up on YouTube, and suggests future coverage like product launches or companies with happy engineers.


Went 280km/h (174mph) in a Porsche Panamera in Germany!

Stephane BoucherStephane Boucher July 10, 201712 comments

A week at SEGGER’s headquarters in Germany turned into more than a video shoot, it became a look inside a company that clearly runs on passion, trust, and a lot of teamwork. Stephane Boucher also gets an unforgettable autobahn ride in a Porsche Panamera, hitting 280 km/h along the way. Between interviews, B-roll, and a 25th anniversary celebration, he comes away impressed by both the people and the pace.


Going back to Germany!

Stephane BoucherStephane Boucher June 13, 20176 comments

A conference conversation turned into a return trip to Germany for Stephane Boucher, this time to visit SEGGER’s headquarters in Dusseldorf and produce videos. The post shares how a chance introduction at ESC Boston led to the invitation, and it teases coverage from SEGGER’s 25th anniversary celebration. He also invites local tips and customer questions before the trip.


ESC Boston's Videos are Now Up

Stephane BoucherStephane Boucher June 5, 2017

Stephane Boucher shares the videos he produced from ESC Boston, including a short highlight montage, a booth video for DLOGIC, and full talk clips from the conference. He also reflects on what he learned shooting on the show floor, especially the challenge of getting engineers on camera. It’s a quick behind-the-scenes look at technical event videography, with a preview of his next stop in Germany.