Back from ESC Boston
Stephane nearly skipped ESC Boston, but going turned into a productive mix of networking, informal meetups, and on-the-floor filming. He captures candid encounters with speakers and vendors, learns how small shows differ from larger expos, and outlines practical follow-ups like booth highlight videos and speaker hospitality suggestions. The post is an encouraging read for engineers weighing the value of regional conferences and DIY event coverage.
Launch of Youtube Channel: My First Videos - Embedded World 2017
Stephane Boucher turned his Embedded World 2017 trip into a debut YouTube series of short booth highlight videos. He walks through the steep learning curve of trade-show filming, the specific gear he bought and rented to cope with low light and noise, and the practical mistakes he plans to fix. The post lists filmed vendors and asks readers for feedback to improve future episodes.
New Comments System (please help me test it)
DSPRelated just got a practical upgrade, Stephane Boucher has released a new comments system built from his earlier forum work. It supports drag-and-drop or Insert Image uploads, MathML, TeX and ASCIImath rendered by MathJax, syntax-highlighted code via highlight.js, and in-place editing and deletion of comments. Improved email notifications alert authors and commenters to replies, and readers are invited to post test comments and report problems.
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Michael Morris demonstrates a practical DPLL that locks a Direct Digital Synthesizer to a GPS 1PPS signal, achieving sub-microsecond alignment and removing reference-oscillator frequency error. The design uses a Phase-Frequency Detector for 0 degree phase lock, a multiplier-free α-filter, and a limiter to prevent saturation, and includes coast and re-lock logic plus a synthesizable Verilog reference core.
Summer of gateware is coming (again)
Wondering what gateware will come out of this summer? Christopher Felton announces MyHDL is back in Google Summer of Code and has been awarded six student slots. Projects span GEMAC, a Leros tiny processor, JPEG encoder front/backends, RISC-V tooling and HDMI+RISC-V work. Follow along for short project updates and a final summer summary.
Data Types for Control & DSP
Control engineers often default to double precision, but Tim Wescott shows that choice can waste CPU cycles on embedded targets. He separates numeric representation into floating point, integer, and fixed-point, then walks through the tradeoffs, including quantization, overflow, and performance. A concrete PID example highlights why integrator precision and ADC scaling should drive your choice of data type rather than habit.
3 Good News
Stephane Boucher reports three quick wins for the EmbeddedRelated community: two sponsors have seeded a $1,000 rewards pool, the site now serves all pages over HTTPS, and the new forums have their first active discussions. If you want a share of the sponsor-funded rewards, jump into the forums and check the Vendors Directory for opportunities. Stay tuned for more updates.
The New Forum is LIVE!
The EmbeddedRelated forum just got a major interface refresh, and Stephane Boucher is rolling it out in beta. The new editor makes it easier to drop in images and files, add LaTeX equations with MathJax, and publish highlighted code snippets with highlight.js. Access is gated by approval for now, mainly to keep trolls, spammers, and bots out.
Running Average
This post shows a lightweight running average variant that cleans up noisy wheel-encoder timing using a shift-based divide-by-8 and a small rounding constant. The filter updates as M1 = M0 + (t0 - A0), where A0 is estimated from the previous average, so each new measurement nudges the estimate rather than immediately replacing it. It trades exact oldest-sample subtraction for low resource cost and strong noise suppression.
Ancient History
Technology moves fast, and the tools, platforms, and assumptions you rely on can become outdated almost overnight. In this reflective post, the author contrasts the rapid evolution of embedded development with the much slower pace of social change, from programming turnaround times to the underrepresentation of women in engineering. It is a reminder to keep learning, but also to think about how we work and who gets included.
Live Streaming from Embedded World!
Stephane Boucher will bring Embedded World to engineers who cannot attend, streaming high-quality HD video from the show floor. He plans to use a professional camera and a device that bonds three internet links to keep the stream stable, and he is coordinating live sessions with vendors and select talks. Read on to learn how to vote for the presentations you want streamed.
Embedded World 2018 - More Videos!
Two cinematic videos from Embedded World 2018 turn the show floor into slow-motion, stabilized footage using a Zhiyun Crane gimbal and a Sony a6300. One is a SEGGER booth highlights piece featuring Rolf Segger and Axel Wolf, the other is a roaming montage with appearances from Jacob Beningo, Micheal Barr, and Alan Hawse. Stephane asks viewers to enable audio and share feedback.
SEGGER's 25th Anniversary Video
Stephane Boucher spent a week at SEGGER's headquarters and distilled that visit into a tight, two-minute 25th anniversary video. The post highlights rising production value, thanks to softbox lighting and a two-camera setup that allows seamless wide-to-tight cuts and emotional close-ups. Stephane invites readers to watch full screen, leave feedback and thumbs-up on YouTube, and suggests future coverage like product launches or companies with happy engineers.
Polynomial Inverse
One of the important steps of computing point addition over elliptic curves is a division of two polynomials.
Windows XP and Win32 - the Platform of the Future!
Victor Yurkovsky makes the contrarian case that an offline Windows XP VM running Win32 is the most practical platform for modern FPGA development. He explains how Xilinx ISE and related tools often behave far better under XP than on modern Linux distributions, and how VirtualBox fixes USB and GUI headaches. If you maintain FPGA toolchains or write compact C/C++ utilities, this retro setup can save time and frustration.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption.
New book on Elliptic Curve Cryptography
New book on Elliptic Curve Cryptography now online. Deep discount for early purchase. Will really appreciate comments on how to improve the book because physical printing won't happen for a few more months. Check it out here: http://mng.bz/D9NA
BGA and QFP at Home 1 - A Practical Guide.
It's a myth that BGAs and fine-pitch QFPs can't be soldered at home. Victor Yurkovsky lays out a practical, no-frills approach for hobbyists to design and assemble FPGA boards using 2-layer PCBs, breakout modules, and low-cost reflow methods like toaster ovens or hotplates. The article focuses on manufacturable PCB choices, netlist-driven workflows, and power/decoupling tactics that make high-density parts approachable for amateurs.
PC and SP for a small CPU
Victor Yurkovsky walks through a compact stack-based CPU idea that tosses the conventional PC register in favor of a return stack living in Xilinx distributed RAM. The clever twist uses the stack memory addressed by SP as the program counter, making calls trivial and keeping the design tiny. The article shows the Verilog stack module and explains the practical tradeoffs of isolating the return stack.
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Victor Yurkovsky extends his sliding-window token machine idea to instruction decoding, showing how 8/9-bit tokens can index shared "Blue" memory as 32-bit literals, call targets, or decoded instructions. The approach makes instructions dynamic entries that slide with the window, enabling rare opcodes to be synthesized on demand and reducing fixed opcode bloat. He also covers the 0-bit window (the stack), FPGA BRAM tagging, and the latency trade-offs.
New Comments System (please help me test it)
DSPRelated just got a practical upgrade, Stephane Boucher has released a new comments system built from his earlier forum work. It supports drag-and-drop or Insert Image uploads, MathML, TeX and ASCIImath rendered by MathJax, syntax-highlighted code via highlight.js, and in-place editing and deletion of comments. Improved email notifications alert authors and commenters to replies, and readers are invited to post test comments and report problems.
How precise is my measurement?
Precision is quantifiable, not guesswork. This post walks through practical, measurement-oriented statistics you can apply to static or dynamic signals to answer the question, "How precise is my measurement?" It focuses on using multiple samples, checking distribution assumptions, and constructing confidence intervals and levels so you can trade measurement time for a desired precision.
Running Average
This post shows a lightweight running average variant that cleans up noisy wheel-encoder timing using a shift-based divide-by-8 and a small rounding constant. The filter updates as M1 = M0 + (t0 - A0), where A0 is estimated from the previous average, so each new measurement nudges the estimate rather than immediately replacing it. It trades exact oldest-sample subtraction for low resource cost and strong noise suppression.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
Sensors Expo - Trip Report & My Best Video Yet!
Stephane Boucher turns a first-time Sensors Expo visit into a fun travelogue and a polished conference highlights video. He mixes candid trip anecdotes from Moncton to San Jose, electric-scooter discoveries, Santa Cruz detours, Airbnb tips, and on-the-floor expo footage. The post culminates in what he calls his best highlights reel yet, plus a follow-up video focused on embedded and IoT.
Verilog vs VHDL
Muhammad Yasir compares Verilog and VHDL by tracing their history, core features, and global usage to help engineers pick an HDL. The post explains where each language shines: Verilog for concise, low-level IC modeling and faster coding, VHDL for strong typing, packages, and system-level clarity, and it uses Google Trends and market examples to put adoption into context.
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
Michael Morris shows how to pack many asynchronous serial receivers into the area of a single UART by treating FPGA LUTs as writable storage and sharing logic. Using a 4-bit channel counter, microprogrammed state machine, and time-multiplexed baud/sample resources, he fits 16 receive channels (12 used for Caller ID) into a Spartan II XC2S30 and explains input synchronization, filtering, and the multi-channel FIFO approach.
In TCL FPGA Wizards Trust
In TCL FPGA wizards trust. The best way to learn TCL is exposure therapy which we will be doing here using two examples: One for creation of a project with synthesis and implementation steps and another for simulation.
Little to no benefit from C based HLS
Christopher shows why C-based HLS delivers little practical benefit compared with a MyHDL RTL approach, using a Vivado HLS median-filter example. He walks through the sort-network median, compares C and MyHDL implementations, and argues MyHDL is as concise while providing clearer microarchitecture control. The post emphasizes that choosing the right algorithm is the hard part, and HLS won’t replace hardware understanding.
