Crowdfunding Articles?
Many of you have the knowledge and talent to write technical articles that would benefit the EE community. What is missing for most of you though, and very understandably so, is the time and motivation to do it.
But what if you could make some money to compensate for your time spent on writing the article(s)? Would some of you find the motivation and make the time?
I am thinking of implementing a system/mechanism that would allow the EE community to...
Cutting a Path Forward
Introduction
As a newcomer to the community, I thought I would start off by introducing myself, and give a little information about what has drawn me to start working with FPGAs.
My day job is as a professional software developer: Figure out what people want; figure out how to make it happen (if possible); and then wrangle code, databases, networks, and servers into giving the correct responses or actions as necessary.
By night, however, I've been working on my...
How precise is my measurement?
Some might argue that measurement is a blend of skepticism and faith. While time constraints might make you lean toward faith, some healthy engineering skepticism should bring you back to statistics. This article reviews some practical statistics that can help you satisfy one common question posed by skeptical engineers: “How precise is my measurement?” As we’ll see, by understanding how to answer it, you gain a degree of control over your measurement time.
An accurate, precise...Embedded World 2018 - More Videos!
After the interview videos last week, this week I am very happy to release two more videos taken at Embedded World 2018 and that I am proud of.
For both videos, I made extensive use of my two new toys, a Zhiyun Crane Gimbal and a Sony a6300 camera.
The use of a gimbal like the Zhiyun makes a big difference in terms of making the footage look much more stable and cinematographic.
As for the Sony camera, it takes fantastic slow-motion footage and...
Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed
This part in the series will consider the signals, measurements, analyses and configurations for testing high-speed low-latency feedback loops and their controllers. Along with basic test signals, a versatile IFFT signal generation scheme will be discussed and implemented. A simple controller under test will be constructed to demonstrate the analysis principles in preparation for the design and evaluation of specific controllers and closed-loop applications.
Additional design...Embedded World 2018 - The Interviews
Once again this year, I had the chance to go to Embedded World in Nuremberg Germany. And once again this year, I brought my video equipment to try and capture some of the most interesting things at the show.
Something new this year, I asked Jacob Beningo if he would partner with me in doing interviews with a few vendors. I would operate the camera while Jacob would ask the right questions to the vendors to make them talk about the key products/features that...
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator
Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.
This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.
- Part 6: Self-Calibration, Measurements and Signalling (this part)
- Part 5:
Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with application examples will be maintained on the project website here.- Part 5: Some FPGA Aspects (this part)
- Part 4: Engineering of...
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...
Linear Feedback Shift Registers for the Uninitiated, Part II: libgf2 and Primitive Polynomials
Last time, we looked at the basics of LFSRs and finite fields formed by the quotient ring \( GF(2)[x]/p(x) \).
LFSRs can be described by a list of binary coefficients, sometimes referred as the polynomial, since they correspond directly to the characteristic polynomial of the quotient ring.
Today we’re going to look at how to perform certain practical calculations in these finite fields. I maintain a Python library called libgf2,...
Running Average
The running average filter is a useful way to reduce noise in a system. One project I recently worked on required a 4 times frequency output from an encoder input. The problem was the encoder is mounted to the wheel of an old truck and bearing noise was making the original algorithm generate way too many pulses. The original algorithm worked, but the noise on the input made it useless.
I first implemented the moving average based on
Dealing With Fixed Point Fractions
Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow. If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions. When integers overflow, they lose data off the most significant bits. When fractions overflow, they lose data off...
StrangeCPU #1. A new CPU
Summary: In this multi-part series I will share with you a design, implementation notes and code for a slightly different kind of a CPU featuring a novel token machine that resolves an 8-bit token to pretty much any address in a 32-bit or even 64-bit address space, using not much more than an adder.
Table of Contents:- Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes.
Went 280km/h (174mph) in a Porsche Panamera in Germany!
Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos. It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.
Two jobs
For those of you following closely embeddedrelated and the other related sites, you might have noticed that I have been less active for the last couple of months, and I will use this blog post to explain why. The main reason is that I got myself involved into a project that ended up using a better part of my cpu than I originally thought it would.
edit - video of the event:
I currently have two jobs: one as an electrical/dsp engineer recycled as a web publisher and the other...
Using GHDL for interactive simulation under Linux
The opensource and free VHDL simulator 'GHDL' has been out for many years, but like many other opensource tools, it has caught limited attention from the industry. I can hear you thinking: 'If it doesn't cost money, it can't be worth it'. Well, I hope this short overview will change your mind and even whet your appetite for more. Because, using some extensions, you can do some quite funky stuff with it that will save you a lot of debugging work. For example, simulate your real world software...
PC and SP for a small CPU
Ok, let's make a small stack-based CPU.
I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.
Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...
Homebrew CPUs: Messing around with a J1
In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster. I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.
J1 CPUMy hat is off to James Bowman. J1 is pretty cool. It is a stack machine; it executes instructions in one cycle, it is...
Welcoming MANY New Bloggers!
The response to the latest call for bloggers has been amazing and I am very grateful.
In this post I present to you the individuals who, so far (I am still receiving applications at an impressive rate and will update this page as more bloggers are added), have been given access to the blogging interface. I am very pleased with the positive response and I think the near future will see the publication of many great articles, given the quality of the...
Homebrew CPUs: Messing around with a J1
In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster. I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.
J1 CPUMy hat is off to James Bowman. J1 is pretty cool. It is a stack machine; it executes instructions in one cycle, it is...
Spread the Word and Run a Chance to Win a Bundle of Goodies from Embedded World
Do you have a Twitter and/or Linkedin account?
If you do, please consider paying close attention for the next few days to the EmbeddedRelated Twitter account and to my personal Linkedin account (feel free to connect). This is where I will be posting lots of updates about how the EmbeddedRelated.tv live streaming experience is going at Embedded World.
The most successful this live broadcasting experience will be, the better the chances that I will be able to do it...
VGA Output in 7 Slices. Really.
Ridiculous? Read on - I will show you how to generate VGA timing in seven XilinxR Spartan3R slices.Some time ago I needed to output video to a VGA monitor for my Apple ][ FPGA clone. Obviously (I thought), VGA's been done before and all I had to do was find some Verilog code and drop it into my design. As is often the case (with me anyway), the task proved to be very different from my imagined 'couple of hours to integrate the IP'.I found some example code for my board. I...
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Summary:Decoding instructions with a Sliding Window system. 0-Bit Sliding Register Windows.
Table of Contents:- Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes.
- Part 2: Sliding-Window Token Machines, an in-depth exploration of this curious technology; ARM notes.
- Part 3. Instruction Slides - The Strangest CPU Yet! Decoding instructions with a Sliding...
PC and SP for a small CPU
Ok, let's make a small stack-based CPU.
I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.
Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...
Shared-multiplier polyphase FIR filter
Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier
Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.
IntroductionA polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...
Recruiting New Bloggers!
Previous calls for bloggers have been very successful in recruiting some great communicators - Rick Lyons, Jason Sachs, Victor Yurkovsky, Mike Silva, Markus Nentwig, Gene Breniman, Stephen Friederichs,
Verilog vs VHDL
Introduction
Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...
The DSP Online Conference - Right Around the Corner!
It is Sunday night as I write this blog post with a few days to go before the virtual doors of the very first DSP Online Conference open..
It all started with a post in the DSPRelated forum about three months ago. We had just had a blast running the 2020 Embedded Online Conference and we thought it could be fun to organize a smaller event dedicated to the DSP community. So my goal with the post in the forum was to see if...
Dealing With Fixed Point Fractions
Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow. If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions. When integers overflow, they lose data off the most significant bits. When fractions overflow, they lose data off...
New Design - Finally!
For those of you who are familiar with my work, you already know that FPGARelated.com is not the only engineering web site that I publish. I also publish DSPRelated.com and EmbeddedRelated.com. Those two web sites have been on a new design for quite some time now and porting the new design to FPGARelated.com has been on my todo list for too long! I am glad today to announce that I have finally found the time to apply the more modern design to FPGARelated.com.
Thank you...
New Discussion Group: DSP & FPGA
I have just created a new discussion group for engineers implementing DSP functions on FPGAs. The creation of this group has been on my todo list for a long time. If you want to join the group, send a blank email to: fpgadsp-subscribe@yahoogroups.com
As usual, it should take a few weeks before there are enough members for interesting discussions to get started.
