Crowdfunding Articles?
Technical writers in the embedded world often have the expertise, but not always the time or incentive to turn it into a post. Stephane Boucher explores a crowdfunding model for technical articles, where readers would pledge small amounts to back promising abstracts before the writing begins. It is an interesting attempt to create more high quality EE content by paying authors upfront.
Cutting a Path Forward
As a software developer building a drone navigation prototype, the author turned to FPGAs after realizing CPUs and cloud tethering break the "simple, cheap, reliable" constraints. He proposes mapping sensor probabilities into a graph-cut network using negative log-likelihoods to produce risk‑averse, real‑time path planning, aiming for tens of milliseconds. The post explains the graph-cut idea, cites FPGA precedents, and lays out a practical FPGA-focused plan of attack.
How precise is my measurement?
Precision is quantifiable, not guesswork. This post walks through practical, measurement-oriented statistics you can apply to static or dynamic signals to answer the question, "How precise is my measurement?" It focuses on using multiple samples, checking distribution assumptions, and constructing confidence intervals and levels so you can trade measurement time for a desired precision.
Embedded World 2018 - More Videos!
Two cinematic videos from Embedded World 2018 turn the show floor into slow-motion, stabilized footage using a Zhiyun Crane gimbal and a Sony a6300. One is a SEGGER booth highlights piece featuring Rolf Segger and Axel Wolf, the other is a roaming montage with appearances from Jacob Beningo, Micheal Barr, and Alan Hawse. Stephane asks viewers to enable audio and share feedback.
Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed
Built around modest FPGA hardware, this post presents a practical test-bed for evaluating high-speed, low-latency feedback controllers. It covers ADC/DAC specifications, basic and arbitrary test signals, and an IFFT-based generator that can produce thousands of simultaneous tones for rapid Bode, phase, and latency measurements. The article also compares two IFFT strategies, explains turbo sampling, and shows open- and closed-loop test configurations.
Embedded World 2018 - The Interviews
Stephane Boucher brought video gear to Embedded World 2018 and teamed up with Jacob Beningo to capture concise vendor interviews that focus on real product news. The videos showcase Percepio's new Tracealyzer with a drone demo, Intrinsic ID's method for creating device-unique IDs from manufacturing variations, and SEGGER's broader toolset including embOS now certified by TÜV SÜD. Watch for short demos and expert explanations.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.
Self-calibration is the missing piece that turns this mixed-signal hardware from a prototype into a usable instrument. In this installment, the author lays out how the board will measure itself, generate reference signals, and verify ADC and DAC behavior before the low-latency control firmware is built. The result is a practical framework for evaluation, production test, and routine self-test.
Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This installment digs into practical FPGA choices and board-level issues for a low-latency, floating-point feedback controller. It compares a Cyclone V implementation against an older SHARC-based design, quantifies the tradeoff between raw DSP resources and cycle latency, and calls out Gotchas found on the BeMicro CV A9 evaluation card. Engineers get concrete prompts for where to optimize: clocking, DSP-block use, I/O standards, and algorithm partitioning.
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
This installment follows the hardware from concept to first power-up for a low-latency feedback controller and arbitrary circuit emulator. It walks through the practical engineering steps, from requirements, block diagrams, and issue tracking to component selection, simulation, PCB planning, purchasing, and staged bring-up. The result is a realistic look at how careful due diligence and a few trade-offs turned a research idea into working evaluation hardware.
Why I would choose an FPGA development board?
FPGA boards are the smarter choice for hands-on learning and flexible hardware design. Compared with microcontroller dev boards, they let you run many hardware tasks in parallel, reuse the same HDL across different vendors, and even host soft-core microcontrollers inside the fabric. This post walks through those practical advantages and points out modern low-cost boards that make FPGAs accessible for students and engineers.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption.
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
Michael Morris shows how to pack many asynchronous serial receivers into the area of a single UART by treating FPGA LUTs as writable storage and sharing logic. Using a 4-bit channel counter, microprogrammed state machine, and time-multiplexed baud/sample resources, he fits 16 receive channels (12 used for Caller ID) into a Spartan II XC2S30 and explains input synchronization, filtering, and the multi-channel FIFO approach.
Polynomial Math
This post walks through squaring and inversion in a tiny finite field to make ECC math tangible. Using GF(2^5) with primitive polynomial beta^5 + beta^2 + 1 it shows why squaring cancels cross terms so you only need half the lookup table, and how Fermat exponentiation computes inverses via repeated squarings and multiplies. It also demonstrates the Extended Euclid polynomial inverse and compares FPGA and CPU tradeoffs.
I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
Welcoming MANY New Bloggers!
A big influx of new voices just joined DSPRelated, and Stephane Boucher introduces the growing roster of contributors and their backgrounds. The post lists dozens of newly approved bloggers, highlights the range of DSP and embedded expertise they bring, and asks readers to leave constructive feedback on posts. It also explains why some applicants may not have been accepted yet and how to apply properly.
Homebrew CPUs: Messing around with a J1
Victor Yurkovsky takes James Bowman's compact J1 stack CPU and starts hacking: he trims the ALU, replaces the barrel shifter with simpler shifts, and experiments with dual stacks and memory/IO feeding directly into the ALU. The article walks through small, practical changes that cut logic, add instructions, and boost timing on Spartan-6. It's a hands-on tour that shows how approachable homebrew CPUs can be.
Use Microprogramming to Save Resources and Increase Functionality
Microprogramming can rescue an overfull FPGA, Michael Morris shows, by compressing control logic and time-multiplexing FIFO storage. He replaces an ABEL state machine with a small microprogram ROM that uses block RAM for deep Rx/Tx FIFOs and LUT RAM for pointers and counters, freeing about 25 percent of the device. The article includes Verilog comparisons, resource tables, and a microassembler link to reproduce the approach.
Free Goodies from Embedded World - Full Inventory and Upcoming Draw Live-Streaming Date
Stephane came back from Embedded World with a massive haul of development kits, tools and swag and decided to give it away to multiple winners. Read the full inventory, learn how to enter by liking or sharing the LinkedIn and Twitter posts, and tune in Friday March 29 at 1pm EST on EmbeddedRelated.tv for the live draw where winners will pick their prizes.
Spread the Word and Run a Chance to Win a Bundle of Goodies from Embedded World
EmbeddedRelated is turning Embedded World into a live-streaming experiment, and the more engineers help spread the word, the better the coverage could get. Stephane Boucher is asking readers to follow updates on Twitter and LinkedIn, where every like, share, or repost adds another chance to win a box of vendor goodies. The prize mix includes t-shirts, dev kits, gadgets, and plenty of pens.
The DSP Online Conference - Right Around the Corner!
Three months after a forum post, Stephane Boucher and Jacob Beningo pulled together the DSP Online Conference, a two-day virtual event featuring 14 talks from leading DSP experts. Most sessions are 30 to 60 minutes with a 30-minute Zoom Q&A, while extended deep dives from speakers like fred harris are included. Registered attendees get one-year on-demand access, and free or reduced passes are available.
Shared-multiplier polyphase FIR filter
One multiplier and a dual-port RAM can implement an arbitrary m/n polyphase FIR resampler on an FPGA, Markus Nentwig demonstrates. The post focuses on practical implementation details, including a parametrized Verilog design, pipelined MAC control, and a Matlab testbench for verification. It shows how bank indexing and pipeline delay compensation let you multiplex many coefficient banks efficiently for resource-constrained FPGA designs.
Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
Homebrew CPUs: Messing around with a J1
Victor Yurkovsky takes James Bowman's compact J1 stack CPU and starts hacking: he trims the ALU, replaces the barrel shifter with simpler shifts, and experiments with dual stacks and memory/IO feeding directly into the ALU. The article walks through small, practical changes that cut logic, add instructions, and boost timing on Spartan-6. It's a hands-on tour that shows how approachable homebrew CPUs can be.
StrangeCPU #2. Sliding Window Token Machines
Victor Yurkovsky walks through a surprising CPU design that expands tiny 8/9-bit tokens into full 32-bit call targets using a sliding-window pointer table. The article explains the red/blue memory model, compilation tradeoffs like table overrun and under-run, literal factoring, FPGA scaling, and even includes an ARM Cortex-M implementation snippet to show how the interpreter works in practice.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
Two jobs
Stephane Boucher explains why EmbeddedRelated went quiet for a few months after a volunteer project demanded more of his time. He and his wife organized a clown-gymnastics show with 15 kids, sold more than 700 of 800 tickets, and raised $2,700 for the Tree of Hope. Now the shows are done and he plans to resume regular posting with new site features.
Inside the Spartan-6: Using LUTs to optimize circuits
Victor Yurkovsky hit poor synthesis packing while building a J1 CPU on Spartan-6 and traced the problem to an 18-bit logic ALU that mapped to many slices. He demonstrates a practical fix: instantiate LUT6 primitives with carefully chosen INIT values, then use RLOC placement to stack the per-bit LUTs and collapse the design down to five slices. This is a hands-on guide to Xilinx-specific optimization when synthesis falls short.
Square root in fixed point VHDL
In this blog we will design and implement a fixed point square root function in VHDL. The algorithm is based on the recursive Newton Raphson inverse square root algorithm and the implementation offers parametrizable pipeline depth, word length and the algorithm is built with VHDL records and procedures for easy use.
New Design - Finally!
Stephane has finally applied a modern design to FPGARelated.com, bringing the site in line with DSPRelated.com and EmbeddedRelated.com. After a long todo list the refreshed layout and updated styling are live, promising a cleaner, more consistent experience across his engineering sites. Drop by to explore the new look and share feedback with the author.
New Discussion Group: DSP & FPGA
Stephane Boucher has launched a new discussion group for engineers implementing DSP functions on FPGAs. It is meant to become a focused place for sharing ideas, but he notes it may take a few weeks before enough members join for the discussion to really get going. If FPGA-based DSP is your thing, this is an open invitation to get involved early.
