Spread the Word and Run a Chance to Win a Bundle of Goodies from Embedded World
EmbeddedRelated is turning Embedded World into a live-streaming experiment, and the more engineers help spread the word, the better the coverage could get. Stephane Boucher is asking readers to follow updates on Twitter and LinkedIn, where every like, share, or repost adds another chance to win a box of vendor goodies. The prize mix includes t-shirts, dev kits, gadgets, and plenty of pens.
Launch of EmbeddedRelated.tv
Stephane Boucher launches EmbeddedRelated.tv to host live broadcasts from Embedded World, starting next week. The site will show a constantly evolving schedule, a Live! tab to find ongoing streams, and ad-hoc demos added from the show floor. Expect schedule conflicts and small hiccups, and plan to refresh the page and join the forum thread for real-time updates and feedback.
Live Streaming from Embedded World!
Stephane Boucher will bring Embedded World to engineers who cannot attend, streaming high-quality HD video from the show floor. He plans to use a professional camera and a device that bonds three internet links to keep the stream stable, and he is coordinating live sessions with vendors and select talks. Read on to learn how to vote for the presentations you want streamed.
What to See at Embedded World 2019
Skip the overwhelm at Embedded World 2019, Stephane Boucher lays out a practical preview of what to see and how to prioritize your time. The post helps embedded engineers focus on demos, vendor booths, and sessions that matter without getting lost on the show floor. Read it to plan a short, efficient visit that maximizes technical takeaways and networking opportunities.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Sensors Expo - Trip Report & My Best Video Yet!
Stephane Boucher turns a first-time Sensors Expo visit into a fun travelogue and a polished conference highlights video. He mixes candid trip anecdotes from Moncton to San Jose, electric-scooter discoveries, Santa Cruz detours, Airbnb tips, and on-the-floor expo footage. The post culminates in what he calls his best highlights reel yet, plus a follow-up video focused on embedded and IoT.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!
Stephane Boucher is heading to Sensors Expo in San Jose for the first time, and he is bringing cameras to capture demos and build a highlights video. He is also looking for roommates for a roomy Airbnb near the convention center, plus local tips for making the most of a free day in the Bay Area. If you are attending, there is also a registration discount code and a VIP pass giveaway in the mix.
Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA
Sriyash Caculo is building a bridge between filter design and hardware by implementing digital filter blocks in MyHDL and integrating them with PyFDA as part of a Google Summer of Code project. The work aims to convert PyFDA floating point designs into fixed point MyHDL blocks that automatically generate VHDL or Verilog, with tests and tutorials to ensure correctness and usability.
Choosing an Implementation Approach
I outline why I chose a CPU-like Graph Cut Processing Unit for FPGA-based graph-cut work, contrasting whole-problem and streaming approaches from the literature. The plan maps push-relabel style augmenting-path iterations to a simple GCPU state machine and pseudocode, prioritizing staged, testable development now and leaving highly parallel streaming scaling for later.
Inside the Spartan-6: Using LUTs to optimize circuits
Victor Yurkovsky hit poor synthesis packing while building a J1 CPU on Spartan-6 and traced the problem to an 18-bit logic ALU that mapped to many slices. He demonstrates a practical fix: instantiate LUT6 primitives with carefully chosen INIT values, then use RLOC placement to stack the per-bit LUTs and collapse the design down to five slices. This is a hands-on guide to Xilinx-specific optimization when synthesis falls short.
Mastering Modern FPGA Skills for Engineers
In the rapidly evolving tech industry, engineers must acquire proficiency in modern FPGA skills. These skills empower engineers to optimize designs, minimize resource usage, and efficiently address FPGA design challenges while ensuring functionality, security, and compliance.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.
Data Types for Control & DSP
Control engineers often default to double precision, but Tim Wescott shows that choice can waste CPU cycles on embedded targets. He separates numeric representation into floating point, integer, and fixed-point, then walks through the tradeoffs, including quantization, overflow, and performance. A concrete PID example highlights why integrator precision and ADC scaling should drive your choice of data type rather than habit.
Back from Embedded World 2019 - Funny Stories and Live-Streaming Woes
Stephane Boucher tried live-streaming multiple talks from Embedded World 2019 and turned a chaotic experiment into a useful set of lessons for embedded engineers. Between broken tripods, flaky venue WiFi, tricky German SIM purchases, and audio nightmares, he learned practical fixes for reliable streams and better video quality. Read this if you want candid, tactical advice on streaming hardware, connectivity, and on-site troubleshooting.
New book on Elliptic Curve Cryptography
New book on Elliptic Curve Cryptography now online. Deep discount for early purchase. Will really appreciate comments on how to improve the book because physical printing won't happen for a few more months. Check it out here: http://mng.bz/D9NA
Jumping from MCUs to FPGAs - 5 things you need to know
Are you a microcontroller expert beckoned by the siren song of the FPGA? Not long ago, that was me. FPGA-expert friends of mine regularly extolled the virtues of these mysterious components and I wanted in. When I made the leap, I found a world seemingly very familiar, but in reality, vastly different. I found that my years of C programming and microcontroller use often gave pre preconceived interpretations of FPGA resource material which resulted in eye-roll class mistakes in my code. I’ve gleaned five things of vital importance to help you make that transition faster than I did.
Free Goodies from Embedded World - What to Do Next?
Stephane Boucher went on a hunt for free stuff at Embedded World to assemble a giveaway bundle for a lucky reader. This short update shares that haul and asks the embedded community for ideas on what to do next. It is a conversational call for suggestions, aiming to turn conference swag into a useful prize.
Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
This article digs into practical sampled-data issues you must address when building feedback controllers for circuit emulation. It highlights a common MATLAB versus Simulink discrepancy caused by DAC holding, explains why FOH (ramp-invariant) c2d conversion matters, and surveys latency, bit depth, filter and precision trade-offs. It also lists candidate ADCs, DACs and FPGAs used in a real evaluation platform to guide hardware choices.
An Editor for HDLs
If you prefer Notepad++ over Emacs, Dave Vandenbout shows how to turn it into a capable HDL editor using templates, a Perl package generator, and Emacs run in batch mode for beautification. He covers FingerText snippets for VHDL skeletons, binding a Perl script to auto-create/update package component declarations, and invoking Emacs from a hotkey to format files with one keystroke.
A New Related Site!
The post announces the launch of MLRelated, a new Related site dedicated to machine learning and deep learning. It positions MLRelated as complementary to existing Related sites by highlighting cross-cutting interests: TinyML for embedded developers, machine/deep learning applications in signal processing, and FPGA-based AI/ML implementations. The new site debuts with a modest amount of content and is expected to expand rapidly through contributions from the Related community in the form of blogs, forum threads, and webinars. The author invites readers to report navigation errors, share feedback, and propose ideas to help steer MLRelated into a practical, community-driven resource for researchers and practitioners in ML and adjacent domains.
Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm
Michael Morris presents a practical, FPGA-friendly fixed-point implementation of the Goldschmidt algorithm to compute sqrt and 1/sqrt. The post shows how an msb-indexed Y_est table and an N_adj scaling factor produce a reliable initial inverse-square-root estimate for an FP32B16 format, enabling five-iteration convergence. It also covers fixed-point normalization, multiplier/shift tradeoffs, and why this fits a real-time motion-controller use case.
Oscilloscope Dreams
Jason Sachs walks through practical oscilloscope buying criteria for embedded engineers, focusing on bandwidth, channel count, hi-res acquisition, and probing. He explains why mixed-signal scopes and hi-res mode matter, when a 100 MHz scope is sufficient and when to keep a higher-bandwidth instrument, and how probe grounding and waveform export can ruin measurements. Real-world brand notes and try-before-you-buy advice round out the guidance.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Elliptic Curve Cryptography - Basic Math
An introduction to the math of elliptic curves for cryptography. Covers the basic equations of points on an elliptic curve and the concept of point addition as well as multiplication.
Recruiting New Bloggers!
EmbeddedRelated is expanding its blogging team, and Stephane Boucher is inviting engineers, students, hobbyists, and researchers to contribute. He points to the success of earlier contributors and says the community has already read their articles more than 1,250,000 times. If you have knowledge to share, this post explains how to pitch a topic and get started.
Signed serial-/parallel multiplication
Struggling with costly wide adders for signed multiplication on FPGAs? Markus Nentwig unpacks a neat bit-level trick that turns two's-complement signed-signed multiplication into a serial-parallel routine using only a one-bit wider adder. Learn how flipping sign bits and a small, controlled constant cancel lets you avoid full sign-extension, and get a parametrized Verilog RTL plus synthesis notes to try it yourself.
Went 280km/h (174mph) in a Porsche Panamera in Germany!
A week at SEGGER’s headquarters in Germany turned into more than a video shoot, it became a look inside a company that clearly runs on passion, trust, and a lot of teamwork. Stephane Boucher also gets an unforgettable autobahn ride in a Porsche Panamera, hitting 280 km/h along the way. Between interviews, B-roll, and a 25th anniversary celebration, he comes away impressed by both the people and the pace.
Discrete-Time PLLs, Part 1: Basics
In this series of tutorials on discrete-time PLLs we will be focusing on Phase-Locked Loops that can be implemented in discrete-time signal proessors such as FPGAs, DSPs and of course, MATLAB.
Back from ESC Boston
Stephane nearly skipped ESC Boston, but going turned into a productive mix of networking, informal meetups, and on-the-floor filming. He captures candid encounters with speakers and vendors, learns how small shows differ from larger expos, and outlines practical follow-ups like booth highlight videos and speaker hospitality suggestions. The post is an encouraging read for engineers weighing the value of regional conferences and DIY event coverage.
Launch of Youtube Channel: My First Videos - Embedded World 2017
Stephane Boucher turned his Embedded World 2017 trip into a debut YouTube series of short booth highlight videos. He walks through the steep learning curve of trade-show filming, the specific gear he bought and rented to cope with low light and noise, and the practical mistakes he plans to fix. The post lists filmed vendors and asks readers for feedback to improve future episodes.
New Comments System (please help me test it)
DSPRelated just got a practical upgrade, Stephane Boucher has released a new comments system built from his earlier forum work. It supports drag-and-drop or Insert Image uploads, MathML, TeX and ASCIImath rendered by MathJax, syntax-highlighted code via highlight.js, and in-place editing and deletion of comments. Improved email notifications alert authors and commenters to replies, and readers are invited to post test comments and report problems.
3 Good News
Stephane Boucher reports three quick wins for the EmbeddedRelated community: two sponsors have seeded a $1,000 rewards pool, the site now serves all pages over HTTPS, and the new forums have their first active discussions. If you want a share of the sponsor-funded rewards, jump into the forums and check the Vendors Directory for opportunities. Stay tuned for more updates.
The New Forum is LIVE!
The EmbeddedRelated forum just got a major interface refresh, and Stephane Boucher is rolling it out in beta. The new editor makes it easier to drop in images and files, add LaTeX equations with MathJax, and publish highlighted code snippets with highlight.js. Access is gated by approval for now, mainly to keep trolls, spammers, and bots out.
Helping New Bloggers to Break the Ice: A New Ipad Pro for the Author with the Best Article!
Breaking the ice can be tough. Over the years, many individuals have asked to be given access to the blogging interface only to never post an article.
Welcoming MANY New Bloggers!
A big influx of new voices just joined DSPRelated, and Stephane Boucher introduces the growing roster of contributors and their backgrounds. The post lists dozens of newly approved bloggers, highlights the range of DSP and embedded expertise they bring, and asks readers to leave constructive feedback on posts. It also explains why some applicants may not have been accepted yet and how to apply properly.
Recruiting New Bloggers!
EmbeddedRelated is expanding its blogging team, and Stephane Boucher is inviting engineers, students, hobbyists, and researchers to contribute. He points to the success of earlier contributors and says the community has already read their articles more than 1,250,000 times. If you have knowledge to share, this post explains how to pitch a topic and get started.
Two jobs
Stephane Boucher explains why EmbeddedRelated went quiet for a few months after a volunteer project demanded more of his time. He and his wife organized a clown-gymnastics show with 15 kids, sold more than 700 of 800 tickets, and raised $2,700 for the Tree of Hope. Now the shows are done and he plans to resume regular posting with new site features.
FPGA Bloggers Needed - New Reward System
You can earn up to $500 for a single FPGA blog post on FPGARelated. Stephane Boucher announces a new pageview-based reward system that pays $25 for every 250 unique pageviews, capped at $500 when a post reaches 5,000 views. If you write about Verilog, VHDL, or FPGA design and want to share expertise while getting paid, fill the short application form to apply.
