Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
This article digs into practical sampled-data issues you must address when building feedback controllers for circuit emulation. It highlights a common MATLAB versus Simulink discrepancy caused by DAC holding, explains why FOH (ramp-invariant) c2d conversion matters, and surveys latency, bit depth, filter and precision trade-offs. It also lists candidate ADCs, DACs and FPGAs used in a real evaluation platform to guide hardware choices.
Finally got a drone!
Stephane Boucher finally bought a DJI Phantom 4 and found it does more than boost his video production value, it’s also hugely fun to fly. He used the drone for an aerial shot at SEGGER’s anniversary and for a beach project where kids drew a turtle while a separate camera captured a side timelapse. The post highlights creative shot combinations and a reminder to fly where it is legal.
Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples
An engineer's guide to building ideal continuous-time models for hardware emulation, using TINA Spice, MATLAB and Simulink to validate controller and circuit behavior. The article shows how a passive R-C network can be emulated by an amplifier, a current measurement and a summer, with Spice, MATLAB and Simulink producing coincident Bode responses. Small phase differences between MATLAB and Simulink are noted, and sampled-data issues are slated for the next installment.
Feedback Controllers - Making Hardware with Firmware. Part I. Introduction
This first post kicks off a series on using DSP and feedback control with mixed-signal electronics and FPGAs to emulate two-terminal circuits and create low latency controllers. It frames circuit emulation as a feedback problem, highlights latency as the key practical constraint, and outlines the planned evaluation hardware, target devices, and software tools that will be used in later MATLAB/Simulink and FPGA work.
SEGGER's 25th Anniversary Video
Stephane Boucher spent a week at SEGGER's headquarters and distilled that visit into a tight, two-minute 25th anniversary video. The post highlights rising production value, thanks to softbox lighting and a two-camera setup that allows seamless wide-to-tight cuts and emotional close-ups. Stephane invites readers to watch full screen, leave feedback and thumbs-up on YouTube, and suggests future coverage like product launches or companies with happy engineers.
Linear Feedback Shift Registers for the Uninitiated, Part II: libgf2 and Primitive Polynomials
Jason Sachs digs into practical finite-field arithmetic for LFSRs, using his libgf2 Python library as the hands-on guide. He shows how to test whether a polynomial is primitive, why that matters for maximal-length sequences, and how the library implements addition, multiplication, exponentiation, and shifts over GF(2). The post is both a math refresher and a code walkthrough for engineers who want to compute with LFSRs instead of just talk about them.
Went 280km/h (174mph) in a Porsche Panamera in Germany!
A week at SEGGER’s headquarters in Germany turned into more than a video shoot, it became a look inside a company that clearly runs on passion, trust, and a lot of teamwork. Stephane Boucher also gets an unforgettable autobahn ride in a Porsche Panamera, hitting 280 km/h along the way. Between interviews, B-roll, and a 25th anniversary celebration, he comes away impressed by both the people and the pace.
Linear Feedback Shift Registers for the Uninitiated, Part I: Ex-Pralite Monks and Finite Fields
Jason Sachs demystifies linear feedback shift registers with a practical, bitwise view and the algebra that explains why they work. Readable examples compare Fibonacci and Galois implementations, show a simple software implementation, and reveal the correspondence between N-bit Galois LFSRs and GF(2^N) so you can pick taps and reason about maximal-length pseudorandom sequences.
Going back to Germany!
A conference conversation turned into a return trip to Germany for Stephane Boucher, this time to visit SEGGER’s headquarters in Dusseldorf and produce videos. The post shares how a chance introduction at ESC Boston led to the invitation, and it teases coverage from SEGGER’s 25th anniversary celebration. He also invites local tips and customer questions before the trip.
ESC Boston's Videos are Now Up
Stephane Boucher shares the videos he produced from ESC Boston, including a short highlight montage, a booth video for DLOGIC, and full talk clips from the conference. He also reflects on what he learned shooting on the show floor, especially the challenge of getting engineers on camera. It’s a quick behind-the-scenes look at technical event videography, with a preview of his next stop in Germany.
BGA and QFP at Home 1 - A Practical Guide.
It's a myth that BGAs and fine-pitch QFPs can't be soldered at home. Victor Yurkovsky lays out a practical, no-frills approach for hobbyists to design and assemble FPGA boards using 2-layer PCBs, breakout modules, and low-cost reflow methods like toaster ovens or hotplates. The article focuses on manufacturable PCB choices, netlist-driven workflows, and power/decoupling tactics that make high-density parts approachable for amateurs.
Homebrew CPUs: Messing around with a J1
Victor Yurkovsky takes James Bowman's compact J1 stack CPU and starts hacking: he trims the ALU, replaces the barrel shifter with simpler shifts, and experiments with dual stacks and memory/IO feeding directly into the ALU. The article walks through small, practical changes that cut logic, add instructions, and boost timing on Spartan-6. It's a hands-on tour that shows how approachable homebrew CPUs can be.
Went 280km/h (174mph) in a Porsche Panamera in Germany!
A week at SEGGER’s headquarters in Germany turned into more than a video shoot, it became a look inside a company that clearly runs on passion, trust, and a lot of teamwork. Stephane Boucher also gets an unforgettable autobahn ride in a Porsche Panamera, hitting 280 km/h along the way. Between interviews, B-roll, and a 25th anniversary celebration, he comes away impressed by both the people and the pace.
Signed serial-/parallel multiplication
Struggling with costly wide adders for signed multiplication on FPGAs? Markus Nentwig unpacks a neat bit-level trick that turns two's-complement signed-signed multiplication into a serial-parallel routine using only a one-bit wider adder. Learn how flipping sign bits and a small, controlled constant cancel lets you avoid full sign-extension, and get a parametrized Verilog RTL plus synthesis notes to try it yourself.
Three more things you need to know when transitioning from MCUs to FPGAs
Take a look at three more important difference between FPGAs and MCUs: "code reuse" vs templating, metastability and blocking vs. non-blocking operations.
Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed
Built around modest FPGA hardware, this post presents a practical test-bed for evaluating high-speed, low-latency feedback controllers. It covers ADC/DAC specifications, basic and arbitrary test signals, and an IFFT-based generator that can produce thousands of simultaneous tones for rapid Bode, phase, and latency measurements. The article also compares two IFFT strategies, explains turbo sampling, and shows open- and closed-loop test configurations.
Shared-multiplier polyphase FIR filter
One multiplier and a dual-port RAM can implement an arbitrary m/n polyphase FIR resampler on an FPGA, Markus Nentwig demonstrates. The post focuses on practical implementation details, including a parametrized Verilog design, pipelined MAC control, and a Matlab testbench for verification. It shows how bank indexing and pipeline delay compensation let you multiplex many coefficient banks efficiently for resource-constrained FPGA designs.
Elliptic Curve Cryptography - Key Exchange and Signatures
Elliptic curve mathematics over finite fields helps solve the problem of exchanging secret keys for encrypted messages as well as proving a specific person signed a particular document. This article goes over simple algorithms for key exchange and digital signature using elliptic curve mathematics. These methods are the essence of elliptic curve cryptography (ECC) used in applications such as SSH, TLS and HTTPS.
New Comments System (please help me test it)
DSPRelated just got a practical upgrade, Stephane Boucher has released a new comments system built from his earlier forum work. It supports drag-and-drop or Insert Image uploads, MathML, TeX and ASCIImath rendered by MathJax, syntax-highlighted code via highlight.js, and in-place editing and deletion of comments. Improved email notifications alert authors and commenters to replies, and readers are invited to post test comments and report problems.
Back from ESC Boston
Stephane nearly skipped ESC Boston, but going turned into a productive mix of networking, informal meetups, and on-the-floor filming. He captures candid encounters with speakers and vendors, learns how small shows differ from larger expos, and outlines practical follow-ups like booth highlight videos and speaker hospitality suggestions. The post is an encouraging read for engineers weighing the value of regional conferences and DIY event coverage.
Linear Feedback Shift Registers for the Uninitiated, Part II: libgf2 and Primitive Polynomials
Jason Sachs digs into practical finite-field arithmetic for LFSRs, using his libgf2 Python library as the hands-on guide. He shows how to test whether a polynomial is primitive, why that matters for maximal-length sequences, and how the library implements addition, multiplication, exponentiation, and shifts over GF(2). The post is both a math refresher and a code walkthrough for engineers who want to compute with LFSRs instead of just talk about them.
Square root in fixed point VHDL
In this blog we will design and implement a fixed point square root function in VHDL. The algorithm is based on the recursive Newton Raphson inverse square root algorithm and the implementation offers parametrizable pipeline depth, word length and the algorithm is built with VHDL records and procedures for easy use.
Inside the Spartan-6: Using LUTs to optimize circuits
Victor Yurkovsky hit poor synthesis packing while building a J1 CPU on Spartan-6 and traced the problem to an 18-bit logic ALU that mapped to many slices. He demonstrates a practical fix: instantiate LUT6 primitives with carefully chosen INIT values, then use RLOC placement to stack the per-bit LUTs and collapse the design down to five slices. This is a hands-on guide to Xilinx-specific optimization when synthesis falls short.
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Victor Yurkovsky extends his sliding-window token machine idea to instruction decoding, showing how 8/9-bit tokens can index shared "Blue" memory as 32-bit literals, call targets, or decoded instructions. The approach makes instructions dynamic entries that slide with the window, enabling rare opcodes to be synthesized on demand and reducing fixed opcode bloat. He also covers the 0-bit window (the stack), FPGA BRAM tagging, and the latency trade-offs.
PC and SP for a small CPU
Victor Yurkovsky walks through a compact stack-based CPU idea that tosses the conventional PC register in favor of a return stack living in Xilinx distributed RAM. The clever twist uses the stack memory addressed by SP as the program counter, making calls trivial and keeping the design tiny. The article shows the Verilog stack module and explains the practical tradeoffs of isolating the return stack.
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption.
Spline interpolation
Markus Nentwig provides a cookbook for segmented cubic spline interpolation that turns scattered or noisy data into efficient fixed-point functions. The article shows how to build third-order polynomial segments with explicit value and slope control via basis functions, solve scaling factors by least-squares in Octave/Matlab, and export coefficients for Verilog RTL evaluation using the Horner scheme and practical fixed-point tips.
Welcoming MANY New Bloggers!
A big influx of new voices just joined DSPRelated, and Stephane Boucher introduces the growing roster of contributors and their backgrounds. The post lists dozens of newly approved bloggers, highlights the range of DSP and embedded expertise they bring, and asks readers to leave constructive feedback on posts. It also explains why some applicants may not have been accepted yet and how to apply properly.
Data Types for Control & DSP
Control engineers often default to double precision, but Tim Wescott shows that choice can waste CPU cycles on embedded targets. He separates numeric representation into floating point, integer, and fixed-point, then walks through the tradeoffs, including quantization, overflow, and performance. A concrete PID example highlights why integrator precision and ADC scaling should drive your choice of data type rather than habit.
Running Average
This post shows a lightweight running average variant that cleans up noisy wheel-encoder timing using a shift-based divide-by-8 and a small rounding constant. The filter updates as M1 = M0 + (t0 - A0), where A0 is estimated from the previous average, so each new measurement nudges the estimate rather than immediately replacing it. It trades exact oldest-sample subtraction for low resource cost and strong noise suppression.
